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Signal integrity of transmitted data is critical for achieving highly dense, large-scale superconductor circuits. Transmission line effects, such as signal reflections, are investigated and concepts from microwave circuit theory and conventional digital logic circuits are applied to AQFP circuits. The lossless transmission line model is used for interconnection modelling. The frequency content and timing characteristics of data signals are used to analytically predict a maximum propagation delay of 6.1 ps before failure due to reflections. This coincides well with our own results, and with those obtained in a separate study using simulation techniques. The investigation then extends towards the design of an impedance matching network with the aim of reducing reflections. The input impedance of a standard buffer gate is derived, and then matched to an 8 Ω transmission line. The proposed impedance matching network maintains data signal integrity up to 3 millimetres. Energy analysis of the matching network is also performed and a 36 % increase in length for similar energy consumption is achieved over alternative solutions.

Adiabatic quantum-flux-parametron (AQFP) logic is a superconductor logic family that can operate with low switching energy due to adiabatic switching. In a previous study, we proposed a low-latency clocking scheme called delay-line clocking, in which the latency for each logic operation is determined by the propagation delay of the excitation current. We demonstrated several AQFP logic gates with delay-line clocking and demonstrated a phase skipping operation, in which some of the AQFP buffers for phase synchronization are removed to reduce the junction count and energy dissipation. In the present study, we design and demonstrate an AQFP 8-bit ripple carry adder with delay-line clocking to show that delay-line clocking and the phase skipping operation are applicable to large-scale AQFP circuits. The latency of this adder is 960 ps, which is 40% of that for a conventional design. Moreover, due to the phase skipping operation, the junction count is reduced to approximately 70% of that for the conventional design. We find that this adder can operate at up to 4 GHz. The above results indicate that large-scale AQFP circuits can operate with low latency and low junction count by using delay-line clocking and a phase skipping operation.

Adiabatic quantum-flux-parametron (AQFP) logic is an energy-efficient superconductor logic family that utilizes adiabatic switching of logic gates. At present, a pure inductance is used to model a gate-to-gate interconnection in AQFP logic circuits. However, it is necessary to consider the transmission line effects when the interconnection length becomes long to take into account the propagation delay. This study investigated the transmission line effects of a long gate-to-gate interconnection in AQFP logic circuits. We observed reflection effects in a long transmission line between AQFP gates. These effects induced errors when the interconnection length exceeded several hundred micrometers. We adopted a damping resistance to stabilize the reflection effect to realize an error-free long gate-to-gate interconnection. The circuit simulations confirmed that a damping resistance connected in parallel to the transmission line effectively stabilizes the reflection effect, enabling an interconnection length that is longer than 1 mm. We fabricated AQFP buffer chains that included a long transmission line with and without a parallel damping resistance, and measured their bit error rates. The results showed that the parallel damping resistance effectively improves the bit error rate at high frequencies.

Adiabatic quantum-flux-parametron (AQFP) logic is a promising technology for future energy-efficient, high- performance information processing systems because it has significantly low power consumption due to the adiabatic switching of Josephson junctions. We are developing a high-performance field-programmable gate array (FPGA) using superconducting AQFP circuits to reduce its energy consumption. The all-AQFP FPGA consists of logic blocks, switch blocks, connection blocks, and memory using AQFP circuits. In particular, the memory is composed of AQFP buffer chains, enabling high-density and low-power memory. The switch blocks can perform data routing as well as several logic functions, including majority, and, and or functions, which increases the design flexibility of the all-AQFP FPGA. We fabricated a one-unit all-AQFP FPGA and demonstrated its reconfigurable operation at low speed. It was found that much lower power consumption can be achieved in the new FPGA than in the other superconducting FPGAs.

We study the design and optimization of the Boltzmann machine hardware using superconducting circuits as a new stochastic information processing method. The Boltzmann machine is an artificial neural network of stochastic binary models wherein the energy function is determined by the given set of parameters, and the output is obtained by stochastic state transitions of the system to the energy stable states according to the Boltzmann distribution. By adjusting the set of parameters, arbitrary functions can be embedded in energy-stable states, which have applications in data dimensionality reduction and generative models. The hardware of a Boltzmann machine using superconducting circuits consists of quantum flux parametrons (QFPs), one of the superconducting circuits, magnetically coupled to each other. In this study, we designed the Boltzmann machine hardware in which logic gates such as NOR are embedded in energy-stable states. Furthermore, we applied maximum likelihood estimation (MLE), machine learning method, as an operating-point optimization method, and confirmed the effectiveness of this method in experiments.