Search

Abstract: In this paper, silicon-on-insulator MOSFETs and ring oscillators are, for the first time, fabricated and characterized on 1.5μm-thick multilayered dielectric membranes, as a preliminary study for pressure sensing systems. Stresses were mechanically applied on these membranes, evolving drain current changes up to 5% in the devices characteristics, according to their channel type and orientation with respect to the stress, as well as resonance frequency shifts of −0.8% and +2.5% for the voltage controlled oscillators. Finite element simulations were performed, showing that the stresses are maximized at the center of the membrane anchors and pointing out the location for the devices to provide the best sensitivity. Internal membrane stresses are considered and discussed. [Copyright &y& Elsevier]

This overview discusses the impact of ionizing irradiation on the static, the transient and the low-frequency noise characteristics of deep submicron partially depleted (PD) silicon-on-insulator (SOI) transistors. It is demonstrated that, while from a total ionizing dose (TID) damage viewpoint the technology is suitable for space applications, there is still a marked performance degradation. Evidence is provided that at least two basic mechanisms are involved. One is related to the radiation-induced hole trapping in the field oxide, giving rise to a subthreshold leakage current. In addition, the occurrence of majority carrier injection by electron valence-band (EVB) tunneling gives rise to some unexpected front–back channel coupling effects. A second yet unknown mechanism gives rise to a length-dependent response of the static device parameters, pointing to a laterally non-uniform charging of the gate oxide and/or the silicon body. [Copyright &y& Elsevier]

This work presents a new method to extract the oxide charge densities at front (Qox1) and back (Qox2) interfaces of fully depleted SOI nMOSFETs. The proposed method is based on the influence of the front and back gate voltages on the back and front channel current regime, respectively. To extract Qox2, the drain current curve is measured as a function of the back gate voltage VGB with the front interface inverted. When the back interface condition changes due to the back gate voltage, kinks occur in the front drain current for specific VGB values which are used by the method. Similarly, the back drain current as a function of the front gate voltage VGB with the back interface inverted shows some kinks for specific VGF values which are used by the method to extract Qox1. MEDICI simulations were used to support the analysis and the method was applied experimentally. [Copyright &y& Elsevier]

A novel modification of our “2T” floating-body/gate DRAM cell is described and, via numerical simulations, shown to yield very long charge data retention times under worst-case conditions, as well as good memory performance (i.e., large signal margin and low operating power). Relatively low voltage operation is enabled, thereby implying good cell reliability as well. [ABSTRACT FROM AUTHOR]

A surface-potential-based analytical I-V model of single-gate (SG) silicon-on-insulator (SOI) MOSFETs in full-depletion (FD) mode is proposed and compared with numerical data and Khandelwal's experimental results. An explicit calculation scheme of surface potential, processing high computation accuracy and efficiency, is demonstrated according to the derivation of the coupling relation between surface potential and back-channel potential. The maximum absolute error decreases into 10−7 V scale, and computation efficiency is improved substantially compared with numerical iteration. Depending on the surface potential, the drain current is derived in closed-form and validated by Khandelwal's experimental data. High computation accuracy and efficiency suggest that this analytical I-V model displays great promise for SOI device optimizations and circuit simulations. [ABSTRACT FROM AUTHOR]