Search

In this article, we explored the effect of a single charge trap on the charge stability diagram of the quantum-dot-based single-electron transistor. We investigated anomalies in the coulomb characteristic diagram, system energy, occupation probabilities, and quantum dot conductivity arising from the electrostatic interaction between the main dot and this charge trap. The anomalies were studied for various locations of the trap, mainly when the trap is located at the source or drain sides of the device. A significant enhancement in quantum dot conductivity was observed by bringing the main quantum dot closer to the source and drain with increased coupling capacitors. The trap, capacitively linked to the quantum dot, has two charge states, either empty or occupied by a single electron. Considering various quantum states, we solved the master equation using Fermi's golden rule to obtain tunneling rates and the matrix of tunneling coefficients. Inverting the coefficient matrix allowed us to determine the probability of each quantum state. The results of this analysis have been validated by comparing simulation results with experimental data. In conclusion, our study provides a valuable tool for detecting charge presence in a trap near a quantum dot, potentially applicable for the readout of quantum gates. [ABSTRACT FROM AUTHOR]

—Reversible Logic Gates have become very popular for their uninhibited merits like, low power consumption, low garbage output, decreasing the quantum cost, least propagation delay etc. Several circuits have been designed for reversible logic ICs using conventional CMOS technology. But, as the CMOS technology is suffering from scaling down problems, the researchers have moved themselves towards post CMOS devices for further fabrication of Reversible ICs. Among different post CMOS devices, in SET, electrons are tunnelling through the channel one by one, so it offers ultra-low power dissipation compared to the traditional CMOS though it has high speed, high gain like properties. So the hybridization of CMOS-SET can achieve a useful effect on VLSI design, and the new technology is known as Hybrid CMOS-SET (HCS). But as the Hybrid CMOS-SET requires two distinct software, the HCS macro model has become very useful, as it can be simulated by using a single software. In this present paper, the reversible logic gate has been designed using the HCS macro model and is also being simulated using a single software, MATLAB with SIMULINK, with low power consumption.

Current–voltage characteristics of a quantum dot in double-barrier configuration, as formed in the nanoscale channel of silicon transistors, were analyzed both experimentally and theoretically. Single electron transistors (SET) made in a SOI-FET configuration using silicon quantum dot as well as phosphorus donor quantum dots were experimentally investigated. These devices exhibited a quantum Coulomb blockade phenomenon along with a detectable effect of variable tunnel barriers. To replicate the experimental results, we developed a generalized formalism for the tunnel-barrier dependent quantum Coulomb blockade by modifying the rate-equation approach. We qualitatively replicate the experimental results with numerical calculation using this formalism for two and three energy levels participated in the tunneling transport. The new formalism supports the features of most of the small-scaled SET devices. [ABSTRACT FROM AUTHOR]

The arithmetic logic unit (ALU) is one of the most essential components of any microprocessor or computing system that is capable of performing several arithmetic as well as logic operations. For realizing efficient and high-performance ALU, proper designing, optimum selection of materials and incorporation of advanced devices are utmost important. The single electron transistor (SET) is a prominent advanced device structure for achieving high-end computing system. In this paper, the prospective SET-based ALU is realized to meet next-generation requirements like higher speed, lower power, and volume. Also, the enhancement capability of ALU can be further accomplished by incorporating effective modular design using slice-based approach. The slice-based design approach provides simplicity and extensibility of the design. In this, each slice has the capability to perform arithmetic and logical operations on one-bit input data. Henceforth, cascading of n such slices generates the n-bit ALU. The multiplication operation is executed separately. The incorporation of separate multiplier block aids in achieving fast execution of multiplication operation with a single instruction. The performance of high-end proposed SET-based ALU is compared with the conventional complementary metal oxide semiconductor (CMOS) and 18 nm FinFET technology-based ALU designs. It is observed that the SET-based ALU gives 1.9× lesser delay and 19.8× lower power dissipation as compared to its 16 nm CMOS counterpart. Also, with respect to 18 nm FinFET-based technology, proposed SET-based design out-stands extensively in terms of lower transistor count and power. [ABSTRACT FROM AUTHOR]

Among many emerging nanoelectronic devices, single-electron transistor (SET) is one of the frontier device architectures that can offer high operating speed at an ultra-low power consumption. It exploits controlled electron tunneling to amplify current and retains its scalability even on an atomic scale. A new island based SET device architecture is proposed which is made of monolayer tungsten disulfide nanoribbon (WS2 NR) in zigzag pattern. The quantum physics based analytical model is developed in order to investigate the tunnelling drain current flowing through the proposed WS2 NR SET. It has been observed from the simulation study that the device current did not struggle in the coulomb blockade region whereas outside this region drain current value gradually decreases for longer nanoribbon likely due to formation of wider potential well in the island regime which helps to drop the rate of tunnelling electrons.

Modern quantum device fabrication often requires precisely adding and removing materials in situ at nanoscales, which is challenging for high-quality correlated oxide devices. In this work, we present a novel nanofabrication method that remotely controls the interfacial metal-insulator transition at the LaAlO 3 /SrTiO 3 interface by selectively removing an LaAlO 3 overlayer using a diamond tip. Remarkably, we observe a large force window within which single atomic layer precision of control is achievable. Our results confirm the critical thickness and charge transfer mechanism through a layer-by-layer removal process at the interface. Additionally, high-quality nanodevices, including nanochannels and single electron transistors, are successfully fabricated using this method. This nonvolatile and high-precision nanofabrication method provides a promising oxide platform for quantum engineering by harnessing the rich electron correlations at the nanoscale.

The single electron transistor (SET) is a nanoscale switching device with a simple equivalent circuit. It can work very fast as it is based on the tunneling of single electrons. Its nanostructure contains a quantum dot island whose material impacts on the device operation. Carbon allotropes such as fullerene (C60), carbon nanotubes (CNTs) and graphene nanoscrolls (GNSs) can be utilized as the quantum dot island in SETs. In this study, multiple quantum dot islands such as GNS-CNT and GNS-C60 are utilized in SET devices. The currents of two counterpart devices are modeled and analyzed. The impacts of important parameters such as temperature and applied gate voltage on the current of two SETs are investigated using proposed mathematical models. Moreover, the impacts of CNT length, fullerene diameter, GNS length, and GNS spiral length and number of turns on the SET’s current are explored. Additionally, the Coulomb blockade ranges (CB) of the two SETs are compared. The results reveal that the GNS-CNT SET has a lower Coulomb blockade range and a higher current than the GNS-C60 SET. Their charge stability diagrams indicate that the GNS-CNT SET has smaller Coulomb diamond areas, zero-current regions, and zero-conductance regions than the GNS-C60 SET. [ABSTRACT FROM AUTHOR]

We report on low-temperature noise measurements of a single electron transistor (SET) immersed in superfluid 4He. The device acts as a charge sensitive electrometer able to detect the fluctuations of charged defects in close proximity to the SET. In particular, we measure telegraph switching of the electric current through the device originating from a strongly coupled individual two-level fluctuator. By embedding the device in a superfluid helium immersion cell, we are able to systematically control the thermalizing environment surrounding the SET and investigate the effect of the superfluid on the SET noise performance. We find that the presence of superfluid 4He can strongly suppress the switching rate of the defect by cooling the surrounding phonon bath. [ABSTRACT FROM AUTHOR]

In engineering and science, high operating speed, low power consumption, and high integration density equipment are financially indispensable. Single electron device (SED) is one such equipment. SEDs are capable of controlling the transport of only one electron through the tunneling transistor. It is single electron that is sufficient to store information in SED. Power consumed in the single electron circuit is very low in comparison with CMOS circuits. The processing speed of single electron transistor (SET) based device will be nearly close to electronic speed. SET attracts the researchers, scientists or technologists to design and implement large scale circuits for the sake of the consumption of ultra-low power and its small size. All the incidences for the case of a SETbased circuit happen when only a single electron tunnels through the transistors under the proper applied bias voltage and a small gate voltage or multiple gate voltages. For implementing a single electron transistor based voltmeter circuit, SET would be the best candidate to fulfil the requirements of it. Ultra-low noise is generated during tunneling SEDs. A D Flip-Flop is implemented and based on this, two kinds of registers like sequence register and сode register are made. [ABSTRACT FROM AUTHOR]

Nanotechnology and VLSI goes hand in hand. Modernization of electronics and communication systems has demanded for compactness of the devices with low power and high speed. Conventionally CMOS logic is preferred due to its low power and its high speed benefits. Researches demand a new logic style that can effectively replace conventional CMOS. Many styles including Domino logic are already gaining attention in this regard. The proposed work introduces Single Electron Transistors (SET) instead of NMOS in Pull Down Network and Keeper transistor of Domino Logic. As SETs are predominant in Nanotechnology, when employed in domino logic circuits as a fusion with normal MOS transistors will contribute effectively in terms of area, power and delay. The parameters are estimated with Cadence 45nm (SET- Spice Model) technology. The proposed domino logic architectures come up with an average of 68% energy efficiency when compared with conventional CMOS circuit and its Domino logic predecessors. [ABSTRACT FROM AUTHOR]

A fluorobenzene based single electron transistor (SET) has been investigated for the detection of toxic gases viz. NH3, HCN, AsH3, and COCl2, within the framework of density functional theory (DFT) formalism based first-principles approach. Initially, the adsorption mechanism between the fluorobenzene quantum dot and the toxic gases (NH3, HCN, AsH3, and COCl2) has been analyzed in terms of adsorption energy, distance of adsorption, DOS profiles and the charge transfer analysis. Later, the exclusive property of charge stability diagram of SET has been utilized to provide the necessary electronic fingerprints for detection of toxic gases. The results suggest that the fluorobenzene SET can be a potential sensor for proposed toxic gases based on the wide operational temperature range and high detection ability as witnessed from the electronic fingerprints. [ABSTRACT FROM AUTHOR]

Nanotechnology and VLSI goes hand in hand. Modernization of electronics and communication systems has demanded for compactness of the devices with low power and high speed. Conventionally CMOS logic is preferred due to its low power and its high speed benefits. Researches demand a new logic style that can effectively replace conventional CMOS. Many styles including Domino logic are already gaining attention in this regard. The proposed work introduces Single Electron Transistors (SET) instead of NMOS in Pull Down Network and Keeper transistor of Domino Logic. As SETs are predominant in Nanotechnology, when employed in domino logic circuits as a fusion with normal MOS transistors will contribute effectively in terms of area, power and delay. The parameters are estimated with Cadence 45nm (SET- Spice Model) technology. The proposed domino logic architectures come up with an average of 68% energy efficiency when compared with conventional CMOS circuit and its Domino logic predecessors.

For future nanoelectronic devices – such as room-temperature single electron transistors – the site-controlled formation of single Si nanocrystals (NCs) is a crucial prerequisite. Here, we report an approach to fabricate single Si NCs via medium-energy Si+ or Ne+ ion beam mixing of Si into a buried SiO2 layer followed by thermally activated phase separation. Binary collision approximation and kinetic Monte Carlo methods are conducted to gain atomistic insight into the influence of relevant experimental parameters on the Si NC formation process. Energy-filtered transmission electron microscopy is performed to obtain quantitative values on the Si NC size and distribution in dependence of the layer stack geometry, ion fluence and thermal budget. Employing a focused Ne+ beam from a helium ion microscope, we demonstrate site-controlled self-assembly of single Si NCs. Line irradiation with a fluence of 3000 Ne+/nm2 and a line width of 4 nm leads to the formation of a chain of Si NCs, and a single NC with 2.2 nm diameter is subsequently isolated and visualized in a few nanometer thin lamella prepared by a focused ion beam (FIB). The Si NC is centered between the SiO2 layers and perpendicular to the incident Ne+ beam.

Current mirror is basic building block of amplifier, oscillator and comparator circuit. An ideal current mirror is independent of input power and temperature. The output current is constant mirrored image of input current. In order to avoid wrong equilibrium it must have high output impedance. This can be achieved by using super cascode formation. The single electron coulomb blockade structure provides low voltage operation and scaling of transistor to 10 nm. The Single Electron Transistor (SET) based CM is modeled and analyzed by simulation and the results shows improved performance of CM. [ABSTRACT FROM AUTHOR]

Recent advances demonstrated the feasibility of realizing spin-based quantum computation in Silicon. To make further progress towards a large-scale implementation of spin-based quantum device technologies, a reliable fabrication process with good yield and device uniformity is a crucial requirement. We address this challenge by integrating a prototype spin qubit device in a 300 mm process, using state-of-the-art, CMOS-compatible process steps. We demonstrate well-formed single-electron transistors with a feature size of 50 nm, individual electron controllability and show multi-gate control uniformity from room-down to low-temperature. Dots with charging energies of 1–2 meV and sizes of around 46 nm are estimated, in excellent agreement with design geometry. The noise power spectrum reveals 1/f noise with an amplitude of $2~\mu $ eV at 1 Hz. This successful integration enables further exploration of reproducible Silicon-based spin qubit devices and opens paths for systematic investigation of the performance and scalability of future spin-based qubit devices. [ABSTRACT FROM AUTHOR]

We study the behaviour of a single electron transistor (SET) represented by a dissipative tunnel junction between a pair of quantum dots described by two (possibly, different) Sachdev-Ye-Kitaev (SYK) models. A combined influence of the soft collective charge and energy modes on charge transport is discussed, alongside the competing effects of the Coulomb blockade and emergent Kondo resonances which might all conspire to result in a non-monotonic behaviour of the system's conductance. [ABSTRACT FROM AUTHOR]

In this work, within the framework of the density functional theory, the transport properties of a single-electron transistor (SET) based on metallofullerenes Me@C60 (Me  Li, Na, K) were investigated by simulation. The optimization of Li@C60, Na@C60, K@C60 molecules was carried out using the Perdew-Burke Ernzerhof (PBE) exchange-correlation functional and the generalized gradient approximation (GGA), which allows the most accurate description of such structures. Electrostatic difference potential, molecular energy spectrum, and total energy of a SET based on Me@C60 were calculated. It was found that a SET based on K@C60 is more stable than other considered SETs based on C60, Li@C60, Na@C60. The dependences of the total energy of molecules Me@C60 (Me  Li, Na, K) on their total charge are determined, as well as the dependences of the total energy on the gate voltage Me@C60-SET. Due to the instability of the state of small molecules with additional electrons of more than two, during the simulation, the values of – 2, – 1, 0, 1, 2 were chosen as the total electric charges for each molecule. It is shown that the energy of a negatively charged metallofullerene under consideration is lower than that of a neutral one, and vice versa, the energy of a positively charged metallofullerene is greater than that of a neutral one. It was found that at negative transistor gate voltages, positive charge states (+ 1, + 2) are more stable compared to negative charge states (– 1, – 2) due to a shift in the HOMO (highest occupied molecular orbital) and LUMO (lowest unoccupied molecular orbital) with a change in gate voltage. The stability diagrams of SETs based on С60, Me@C60 were analyzed, and it was also shown that the area of the Coulomb diamond SET on the stability diagram depends on the radius of the encapsulated atom. The results obtained can be useful in the calculation of new types of SETs based on metallofullerenes. [ABSTRACT FROM AUTHOR]

Over the past several decades, the performance of existing complementary metal oxide semiconductor (CMOS) technology has been improved by scaling of the CMOS transistors size. However, the performance of nanometre scale CMOS‐based designs is limited due to the short‐channel effect and process variation. The single electron transistor (SET) is a promising advanced nanometre scale device that can mitigate these grave issues. In this study, a novel SET‐based computing system is designed and simulated at a supply voltage of 0.8 V, so that it can be 3D integrated with existing CMOS technology. The SET design parameters are considered based on SET fabricated by nanodamascene process for room temperature operation. The computing system works at frequency of 5 GHz with 2.522 μW power dissipation considering interconnect parasites. The frequency and power dissipation of the SET‐based design is nearly 5 times better and 1.6 times lower than for the same design using 16 nm CMOS technology. The results and various analyses show that the SET‐based systems are highly efficient and hence very effective to incorporate in next‐generation very large scale integration designs. The SET‐based design can be also 3D stacked in tandem with existing CMOS technology to achieve higher benefits in terms of speed, power, density, footprint, and functionality. [ABSTRACT FROM AUTHOR]

We show a manipulation of a single electron at room temperature by controlling Random Telegraph Signals (RTSs) by voltage pulses. Our silicon nanowire triple-gate transistor exhibited RTSs when potential barriers were electrically created by two of the three gates. From the statistics of the signals, we optimized the voltage pulse such that a single electron was intentionally captured in the potential well, and the retention time of approximately 10 ms was observed in this memory operation. This study indicates that a single electron effect can be controllable in a form of RTSs at room temperature by electrically defining a potential well.

This work represents the implementation of a data transfer system using single electron threshold logic based approach. The power consumption of the complete system is 239.2 pW. The complete implementation of the design along with the simulation results of different individual stages is presented in this work. The reliability of the system is one of the main concerns as the background charge fluctuation affects the overall system performance. Considering the background charge to be uniformly and normally distributed the variation of the percentage of reliability along with the variation factor for different type of distributions has been plotted and explained. The stability issue of the circuit has also been discussed using stability plots. [ABSTRACT FROM AUTHOR]

An improved version of the Small-Signal model of a single-electron transistor for high frequency is proposed in this paper. The modification is done by incorporating the parasitic elements for the high-frequency operation of single-electron transistor. The high-frequency operation introduces several spurious elements due to the physical structure and the testing instrument connection to the device under test. The impact of these elements on the matching network is significant but yet unpredictable. The formulation of the Small-Signal model considering the extrinsic and intrinsic elements is elaborated in this literature. The scattering parameters play an important role in the determination of the properties of a transistor working at high frequency. This study is carried out for determining the scattering parameters for single-electron transistor and their relationship with the other intrinsic as well as extrinsic parameters. [ABSTRACT FROM AUTHOR]

Graphene single electron transistor (SET) as a coulomb blockade (CB) device operates based on the quantum mechanical effect. Its desired current is achieved by overcoming the CB energy that depends on the total capacitance of SET. Therefore, small size of graphene quantum capacitance is suitable for SET structure because it plays a dominant role in the total capacitance. In this paper, the density of state (DOS) model of graphene SET is suggested because of its important effect on many physical properties. Furthermore, carrier concentration as a key factor in quantum capacitance is modeled. Finally, the quantum capacitance of graphene SET based on the fundamental parameters is modeled and compared to the experimental data, so an acceptable agreement between them is reported. As a result, silicon SET can be replaced with graphene SET because of its lower quantum capacitance and also higher operation speed than the silicon one. [ABSTRACT FROM AUTHOR]

The single electron transistor (SET) as a fast electronic device is a candidate for future nanoscale circuits because of its low energy consumption, small size and simplified circuit. It consists of source and drain electrodes with a quantum dot (QD) located between them. Moreover, it operates based on the Coulomb blockade (CB) effect. It occurs when the charging energy is greater than the thermal energy. Consequently, this condition limits SET operation at cryogenic temperatures. Hence, using QD arrays can overcome this temperature limitation in SET which can therefore work at room temperature but QD arrays increase the threshold voltage with is an undesirable effect. In this research, fullerene as a zero-dimensional material with unique properties such as quantum capacitance and high critical temperature has been selected for the material of the QDs. Moreover, the current of a fullerene QD array SET has been modeled and its threshold voltage is also compared with a silicon QD array SET. The results show that the threshold voltage of fullerene SET is lower than the silicon one. Furthermore, the comparison study shows that homogeneous linear QD arrays have a lower CB range and better operation than a ring QD array SET. Moreover, the effect of the number of QDs in a QD array SET is investigated. The result confirms that the number of QDs can directly affect the CB range. Moreover, the desired current can be achieved by controlling the applied gate voltage and island diameters in a QD array SET. [ABSTRACT FROM AUTHOR]

The single electron transistor (SET) as a nanoscale transistor operates according to the electron tunneling via two tunnel junctions. Since selecting a suitable island material plays a key role in electron transfer through the tunnel junctions, in this research capped Carbon NanoTube (CNT) is utilized for the SET island which produces the quantum capacitance (C Q ). Its low value decreases the total capacitance (C T ). Subsequently the coulomb blockade (CB) energy and the critical temperature are reduced. Moreover the resistance of the capped CNT as a two dimensional material is very low thus its effect on the total resistance can be neglected. The result of an investigation on the capped CNT SET tunnel junction shows that the tunneling time of electron into or out of island decreases therefore the operation speed of capped CNT SET increases. Furthermore both the resistance and the quantum capacitance are modeled and analyzed. Comparison studies of proposed models indicate that the capped CNT length and applied bias voltage play effective roles on the resistance. Additionally the capped CNT SET is simulated and the capped CNT SET stability diagrams are analyzed. The simulation result shows that the lower capped CNT length exhibits a smaller coulomb diamond regions. The lower CB range leads to faster capped CNT SET and a better reliability can be achieved. [ABSTRACT FROM AUTHOR]

Building low-power and high-density circuits requires new devices, which can be based for example on single electron effects. Single electron transistors (SET), which can operate at room temperature (RT), are candidates with high potential for the post-CMOS era. However, their fabrication relies typically on a statistical fabrication of quantum dots or positioning of nanoparticles or molecules between predefined electrodes. These methods hamper a scaled-up fabrication of RT-SETs. Here, we present a route for reproducible fabrication of RT-SETs on the basis of field-emission scanning probe lithography (FE-SPL) and cryogenic reactive ion etching. Due to the unique capabilities of our FE-SPL tool, enabling pre- and post-inspection of features, highly reliable patterning and precise feature alignment are obtained. The fabricated devices exhibit single electron effects at RT. A combination of this method with nanoimprint lithography would enable a high throughput and reproducible way of RT-SET fabrication. [ABSTRACT FROM AUTHOR]