1,094 results on '"software transactional memory"'
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2. Sharing-Aware Data Mapping in Software Transactional Memory
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Pasqualin, Douglas Pereira, Diener, Matthias, Du Bois, André Rauber, Pilla, Maurício Lima, Goos, Gerhard, Founding Editor, Hartmanis, Juris, Founding Editor, Bertino, Elisa, Editorial Board Member, Gao, Wen, Editorial Board Member, Steffen, Bernhard, Editorial Board Member, Woeginger, Gerhard, Editorial Board Member, Yung, Moti, Editorial Board Member, Orailoglu, Alex, editor, Jung, Matthias, editor, and Reichenbach, Marc, editor
- Published
- 2022
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3. On the impact of mode transition on phased transactional memory performance.
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Munoz Morales, Catalina, Honorio, Bruno, de Carvalho, Joao P.L., Baldassin, Alexandro, and Araujo, Guido
- Subjects
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MEMORY , *COMPUTER software , *HARDWARE - Abstract
Several transactional memory implementations that employ state-of-the-art software and hardware techniques to deliver performance have been investigated in the last decade. Phased-based Transactional Memory (PhTM) systems run transactions in phases, such that all transactions in a phase execute in the same (hardware/software) mode. In PhTM, a runtime monitors the execution and decides when to change all transactions to another execution mode. Identifying the right moment to perform a mode transition is a central problem to achieve performance in PhTM systems. This article analyzes PhTM and provides a characterization of mode transitions and their impact on performance. We consider three PhTM implementations: (i) PhTM*, the first phased-based TM designed; (ii) Commit Throughput Measurement (CTM), a general-purpose runtime; and (iii) GoTM, a Graph-oriented runtime. We conduct a performance analysis to identify the drawbacks and benefits of each PhTM implementation with respect to their associated parameters. Results with speedups of up to 10× over the sequential baseline for CTM show that this mechanism generally shows better performance for a diverse set of applications. • Phased Transactional Memory leverages Hardware and Software implementations. • Transitioning mechanisms decide the proper execution phase. • Performance-based transitioning mechanisms improve overall performance of several applications. [ABSTRACT FROM AUTHOR]
- Published
- 2023
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4. Complete Formal Verification of the PSTM Transaction Scheduler.
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Popovic, Miroslav, Popovic, Marko, Kordic, Branislav, and Huibiao Zhu
- Abstract
State of the art formal verification is based on formal methods and its goal is proving given correctness properties. For example, a PSTM scheduler was modeled in CSP in order to prove deadlock-freeness and starvation-freeness. However, as this paper shows, using solely formal methods is not sufficient. Therefore, in this paper we propose a complete formal verification of trustworthy software, which jointly uses formal verification and formal model testing. As an example, we first test the previous CSP model of PSTM transaction scheduler by comparing the model checker PAT results with the manually derived expected results, for the given test workloads. Next, according to the results of this testing, we correct and extend the CSP model. Finally, using PAT results for the new CSP model, we analyze the performance of the PSTM online transaction scheduling algorithms from the perspective of the relative speedup. [ABSTRACT FROM AUTHOR]
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- 2023
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5. Accelerating Graph Applications Using Phased Transactional Memory
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Morales, Catalina Munoz, Murari, Rafael, de Carvalho, Joao P. L., Honorio, Bruno Chinelato, Baldassin, Alexandro, Araujo, Guido, Goos, Gerhard, Founding Editor, Hartmanis, Juris, Founding Editor, Bertino, Elisa, Editorial Board Member, Gao, Wen, Editorial Board Member, Steffen, Bernhard, Editorial Board Member, Woeginger, Gerhard, Editorial Board Member, Yung, Moti, Editorial Board Member, Sousa, Leonel, editor, Roma, Nuno, editor, and Tomás, Pedro, editor
- Published
- 2021
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6. Characterizing the Sharing Behavior of Applications Using Software Transactional Memory
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Pasqualin, Douglas Pereira, Diener, Matthias, Du Bois, André Rauber, Pilla, Maurício Lima, Goos, Gerhard, Founding Editor, Hartmanis, Juris, Founding Editor, Bertino, Elisa, Editorial Board Member, Gao, Wen, Editorial Board Member, Steffen, Bernhard, Editorial Board Member, Woeginger, Gerhard, Editorial Board Member, Yung, Moti, Editorial Board Member, Wolf, Felix, editor, and Gao, Wanling, editor
- Published
- 2021
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7. Design and implementation of a fully transparent partial abort support for software transactional memory.
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Pellegrini, Alessandro, Di Sanzo, Pierangelo, Piccione, Andrea, and Quaglia, Francesco
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MEMORY ,COMPUTER software ,INFORMATION sharing - Abstract
Software transactional memory (STM) provides synchronization support to ensure atomicity and isolation when threads access shared data in concurrent applications. With STM, shared data accesses are encapsulated within transactions automatically handled by the STM layer. Hence, programmers are not requested to use code‐synchronization mechanisms explicitly, like locking. In this article, we present our experience in designing and implementing a partial abort scheme for STM. The objective of our work is threefold: (1) enabling STM to undo only part of the transaction execution in the case of conflict, (2) designing a scheme that is fully transparent to programmers, thus also allowing to run existing STM applications without modifications, and (3) providing a scheme that can be easily integrated within existing STM runtime environments without altering their internal structure. The scheme we designed is based on automated software instrumentation, which injects into the application capabilities to undo the required portions of transaction executions. Further, it can correctly undo also non‐transactional operations executed on the stack and the heap during a transaction. This capability allows programmers to write transactional code without concerns about the side effects of aborted transactions on both shared and thread‐private data. We integrated and evaluated our partial abort scheme within the TinySTM open‐source library. We analyze the experimental results we achieved with common STM benchmark applications, focusing on the advantages and disadvantages of the proposed solutions for implementing our scheme's different components. Hence, we highlight the appropriate choices and possible solutions to improve partial abort schemes further. [ABSTRACT FROM AUTHOR]
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- 2022
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8. A Parallel Implementation for Cellular Potts Model with Software Transactional Memory
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Tomeu, A. J., Gámez, A., Salguero, A. G., Kacprzyk, Janusz, Series Editor, Pal, Nikhil R., Advisory Editor, Bello Perez, Rafael, Advisory Editor, Corchado, Emilio S., Advisory Editor, Hagras, Hani, Advisory Editor, Kóczy, László T., Advisory Editor, Kreinovich, Vladik, Advisory Editor, Lin, Chin-Teng, Advisory Editor, Lu, Jie, Advisory Editor, Melin, Patricia, Advisory Editor, Nedjah, Nadia, Advisory Editor, Nguyen, Ngoc Thanh, Advisory Editor, Wang, Jun, Advisory Editor, Fdez-Riverola, Florentino, editor, Rocha, Miguel, editor, Mohamad, Mohd Saberi, editor, Zaki, Nazar, editor, and Castellanos-Garzón, José A., editor
- Published
- 2020
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9. MODULARISING VERIFICATION OF DURABLE OPACITY.
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BILA, ELENI, DERRICK, JOHN, DOHERTY, SIMON, DONGOL, BRIJESH, SCHELLHORN, GERHARD, and WEHRHEIM, HEIKE
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DESIGN techniques ,NONVOLATILE memory ,DATA structures ,SHARED workspaces - Abstract
Non-volatile memory (NVM), also known as persistent memory, is an emerging paradigm for memory that preserves its contents even after power loss. NVM is widely expected to become ubiquitous, and hardware architectures are already providing support for NVM programming. This has stimulated interest in the design of novel concepts ensuring correctness of concurrent programming abstractions in the face of persistency and in the development of associated verification approaches. Software transactional memory (STM) is a key programming abstraction that supports concurrent access to shared state. In a fashion similar to linearizability as the correctness condition for concurrent data structures, there is an established notion of correctness for STMs known as opacity. We have recently proposed durable opacity as the natural extension of opacity to a setting with non-volatile memory. Together with this novel correctness condition, we designed a verification technique based on refinement. In this paper, we extend this work in two directions. First, we develop a durably opaque version of NOrec (no ownership records), an existing STM algorithm proven to be opaque. Second, we modularise our existing verification approach by separating the proof of durability of memory accesses from the proof of opacity. For NOrec, this allows us to re-use an existing opacity proof and complement it with a proof of the durability of accesses to shared state. [ABSTRACT FROM AUTHOR]
- Published
- 2022
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10. Efficient Means of Achieving Composability Using Object Based Semantics in Transactional Memory Systems
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Peri, Sathya, Singh, Ajay, Somani, Archit, Hutchison, David, Series Editor, Kanade, Takeo, Series Editor, Kittler, Josef, Series Editor, Kleinberg, Jon M., Series Editor, Mattern, Friedemann, Series Editor, Mitchell, John C., Series Editor, Naor, Moni, Series Editor, Pandu Rangan, C., Series Editor, Steffen, Bernhard, Series Editor, Terzopoulos, Demetri, Series Editor, Tygar, Doug, Series Editor, Podelski, Andreas, editor, and Taïani, François, editor
- Published
- 2019
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11. A Lock Free Approach To Parallelize The Cellular Potts Model: Application To Ductal Carcinoma In Situ
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Tomeu Antonio J. and Salguero Alberto G.
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cellular automata ,cellular potts model ,dcis ,multicore ,parallel ,software transactional memory ,speedup ,Biotechnology ,TP248.13-248.65 - Abstract
In the field of computational biology, in order to simulate multiscale biological systems, the Cellular Potts Model (CPM) has been used, which determines the actions that simulated cells can perform by determining a hamiltonian of energy that takes into account the influence that neighboring cells exert, under a wide range of parameters. There are some proposals in the literature that parallelize the CPM; in all cases, either lock-based techniques or other techniques that require large amounts of information to be disseminated among parallel tasks are used to preserve data coherence. In both cases, computational performance is limited. This work proposes an alternative approach for the parallelization of the model that uses transactional memory to maintain the coherence of the information. A Java implementation has been applied to the simulation of the ductal adenocarcinoma of breast in situ (DCIS). Times and speedups of the simulated execution of the model on the cluster of our university are analyzed. The results show a good speedup.
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- 2020
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12. Teaching Software Transactional Memory in Concurrency Courses with Clojure and Java
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Tomeu, Antonio J., Salguero, Alberto G., Capel, Manuel I., Hutchison, David, Series Editor, Kanade, Takeo, Series Editor, Kittler, Josef, Series Editor, Kleinberg, Jon M., Series Editor, Mattern, Friedemann, Series Editor, Mitchell, John C., Series Editor, Naor, Moni, Series Editor, Pandu Rangan, C., Series Editor, Steffen, Bernhard, Series Editor, Terzopoulos, Demetri, Series Editor, Tygar, Doug, Series Editor, Weikum, Gerhard, Series Editor, Heras, Dora B., editor, Bougé, Luc, editor, Mencagli, Gabriele, editor, Jeannot, Emmanuel, editor, Sakellariou, Rizos, editor, Badia, Rosa M., editor, Barbosa, Jorge G., editor, Ricci, Laura, editor, Scott, Stephen L., editor, Lankes, Stefan, editor, and Weidendorfer, Josef, editor
- Published
- 2018
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13. Parallel fpga routing based on the operator formulation
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Moctar, Yehdhih Ouid Mohammed and Brisk, Philip
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Built Environment and Design ,Architecture ,Engineering ,Electrical Engineering ,Field Programmable Gate Array ,Routing ,Routing Resource Graph ,Maze Expansion ,Irregular Algorithm ,Software Transactional Memory - Abstract
We have implemented an FPGA routing algorithm on a shared memory multi-processor using the Galois API, which offers speculative parallelism in software. The router is a parallel implementation of PathFinder, which is the basis for most commercial FPGA routers. We parallelize the maze expansion step for each net, while routing nets sequentially to limit the amount of rollback that would likely occur due to misspeculation. Our implementation relies on non-blocking priority queues, which use software transactional memory (SMT), to identify the best route for each net. Our experimental results demonstrate scalability for large benchmarks and that the amount of available parallelism depends primarily on the circuit size, not the interdependence of signals. We achieve an average speedup of approximately 3x compared to the most recently published work on parallel multi-threaded FPGA routing, and up to 6x in comparison to the single-threaded router implemented in the publicly available Versatile Place and Route (VPR) framework. Copyright 2014 ACM.
- Published
- 2014
14. Parallel FPGA routing based on the operator formulation
- Author
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Moctar, YOM and Brisk, P
- Subjects
Field Programmable Gate Array ,Routing ,Routing Resource Graph ,Maze Expansion ,Irregular Algorithm ,Software Transactional Memory - Abstract
We have implemented an FPGA routing algorithm on a shared memory multi-processor using the Galois API, which offers speculative parallelism in software. The router is a parallel implementation of PathFinder, which is the basis for most commercial FPGA routers. We parallelize the maze expansion step for each net, while routing nets sequentially to limit the amount of rollback that would likely occur due to misspeculation. Our implementation relies on non-blocking priority queues, which use software transactional memory (SMT), to identify the best route for each net. Our experimental results demonstrate scalability for large benchmarks and that the amount of available parallelism depends primarily on the circuit size, not the interdependence of signals. We achieve an average speedup of approximately 3x compared to the most recently published work on parallel multi-threaded FPGA routing, and up to 6x in comparison to the single-threaded router implemented in the publicly available Versatile Place and Route (VPR) framework. Copyright 2014 ACM.
- Published
- 2014
15. A Distributed Transactional Memory Protocol for Dynamic Networks
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Chatterjee, Moumita, Setua, Sanjit K., Barbosa, Simone Diniz Junqueira, Series editor, Chen, Phoebe, Series editor, Filipe, Joaquim, Series editor, Kotenko, Igor, Series editor, Sivalingam, Krishna M., Series editor, Washio, Takashi, Series editor, Yuan, Junsong, Series editor, Zhou, Lizhu, Series editor, Mandal, J. K., editor, Dutta, Paramartha, editor, and Mukhopadhyay, Somnath, editor
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- 2017
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16. Abort-Free STM: A Non-blocking Concurrency Control Approach Using Software Transactional Memory
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Ghosh, Ammlan, Chaki, Rituparna, Chaki, Nabendu, Kacprzyk, Janusz, Series editor, Pal, Nikhil R., Advisory editor, Bello Perez, Rafael, Advisory editor, Corchado, Emilio S., Advisory editor, Hagras, Hani, Advisory editor, Kóczy, László T., Advisory editor, Kreinovich, Vladik, Advisory editor, Lin, Chin-Teng, Advisory editor, Lu, Jie, Advisory editor, Melin, Patricia, Advisory editor, Nedjah, Nadia, Advisory editor, Nguyen, Ngoc Thanh, Advisory editor, Wang, Jun, Advisory editor, Chaki, Rituparna, editor, Saeed, Khalid, editor, Cortesi, Agostino, editor, and Chaki, Nabendu, editor
- Published
- 2017
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17. Software lock elision for x86 machine code
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Roy, Amitabha and Hand, Steven
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005.3 ,Software transactional memory ,x86 memory consistency model ,Hybrid binary rewriting ,Lock elision - Abstract
More than a decade after becoming a topic of intense research there is no transactional memory hardware nor any examples of software transactional memory use outside the research community. Using software transactional memory in large pieces of software needs copious source code annotations and often means that standard compilers and debuggers can no longer be used. At the same time, overheads associated with software transactional memory fail to motivate programmers to expend the needed effort to use software transactional memory. The only way around the overheads in the case of general unmanaged code is the anticipated availability of hardware support. On the other hand, architects are unwilling to devote power and area budgets in mainstream microprocessors to hardware transactional memory, pointing to transactional memory being a 'niche' programming construct. A deadlock has thus ensued that is blocking transactional memory use and experimentation in the mainstream. This dissertation covers the design and construction of a software transactional memory runtime system called SLE_x86 that can potentially break this deadlock by decoupling transactional memory from programs using it. Unlike most other STM designs, the core design principle is transparency rather than performance. SLE_x86 operates at the level of x86 machine code, thereby becoming immediately applicable to binaries for the popular x86 architecture. The only requirement is that the binary synchronise using known locking constructs or calls such as those in Pthreads or OpenMPlibraries. SLE_x86 provides speculative lock elision (SLE) entirely in software, executing critical sections in the binary using transactional memory. Optionally, the critical sections can also be executed without using transactions by acquiring the protecting lock. The dissertation makes a careful analysis of the impact on performance due to the demands of the x86 memory consistency model and the need to transparently instrument x86 machine code. It shows that both of these problems can be overcome to reach a reasonable level of performance, where transparent software transactional memory can perform better than a lock. SLE_x86 can ensure that programs are ready for transactional memory in any form, without being explicitly written for it.
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- 2011
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18. Chocola: Composable Concurrency Language.
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SWALENS, JANWILLEM, DE KOSTER, JOERI, and DE MEUTER, WOLFGANG
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LANGUAGE & languages , *SEMANTICS , *SURETYSHIP & guaranty - Abstract
Programmers often combine different concurrency models in a single program, in each part of the program using the model that fits best. Many programming languages, such as Clojure, Scala, and Java, cater to this need by supporting different concurrency models. However, existing programming languages often combine concurrency models in an ad hoc way, and the semantics of the combinations are not always well defined. This article studies the combination of three concurrency models: futures, transactions, and actors. We show that a naive combination of these models invalidates the guarantees they normally provide, thereby breaking the assumptions of programmers. Hence, we present Chocola: a unified language of futures, transactions, and actors that maintains the guarantees of all three models wherever possible, even when they are combined. We describe and formalize the semantics of this language and prove the guarantees it provides. We also provide an implementation as an extension of Clojure and demonstrated that it can improve the performance of three benchmark applications for relatively little effort from the developer. [ABSTRACT FROM AUTHOR]
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- 2020
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19. A simulation of distributed STM
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Brkin Dragan, Kordić Branislav, and Popović Miroslav
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cloudSim ,software transactional memory ,distributed systems ,two phase commit protocol ,Electrical engineering. Electronics. Nuclear engineering ,TK1-9971 - Abstract
This paper presents an extension of the IaaS Cloud simulator CloudSim. Computational tasks are modeled in the form of a transaction on a transactional memory and communication between the data center is based on the Two-Phase Commit protocol. The model of the distributed STM prototype is implemented using the extended CloudSim simulator. The obtained results are as expected and in accordance with desired system behavior. The presented results are positive and they stimulate future work in development of distributed STM. [Project of the Serbian Ministry of Education, Science and Technological Development, Grant no. III_044009_2]
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- 2018
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20. Convoider: A Concurrency Bug Avoider Based on Transparent Software Transactional Memory.
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Yu, Zhen, Zuo, Yu, and Zhao, Yong
- Subjects
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TRANSACTION systems (Computer systems) , *SOURCE code , *MEMORY , *COMPUTER software , *PROBLEM solving - Abstract
Software transactional memory is an effective mechanism to avoid concurrency bugs in multi-threaded programs. However, two problems hinder the adoption of traditional such systems in wild world: high human cost for equipping programs with transaction functionality and low compatibility with I/O calls and conditional variables. This paper presents Convoider to try to solve these problems. By intercepting inter-thread operations and designating code among them as transactions in each thread, Convoider automatically transactionalizes target programs without any source code modification and recompiling. By saving/restoring stack frames and CPU registers on beginning/aborting a transaction, Convoider makes execution flow revocable. By turning threads into processes, leveraging virtual memory protection and customizing memory allocation/deallocation, Convoider makes memory manipulations revocable. By maintaining virtual file systems and redirecting I/O operations onto them, Convoider makes I/O effects revocable. By converting lock/unlock operations to no-ops, customizing signal/wait operations on condition variables and committing memory changes transactionally, Convoider makes deadlocks, data races and atomicity violations impossible. Experimental results show that Convoider succeeds in transparently transactionalizing twelve real-world applications and perfectly avoid 94% of thirty-one concurrency bugs used in our experiments. This study can help efficiently transactionalize legacy multi-threaded applications and effectively improve the runtime reliability of them. [ABSTRACT FROM AUTHOR]
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- 2020
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21. A tale of lock-free agents: towards Software Transactional Memory in parallel Agent-Based Simulation.
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Thaler, Jonathan and Siebers, Peer-Olaf
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PARALLEL programming ,PROGRAMMING languages ,DISCRETE event simulation ,MOORE'S law ,COMPUTER software ,MEMORY - Abstract
With the decline of Moore's law and the ever increasing availability of cheap massively parallel hardware, it becomes more and more important to embrace parallel programming methods to implement Agent-Based Simulations (ABS). This has been acknowledged in the field a while ago and numerous research on distributed parallel ABS exists, focusing primarily on Parallel Discrete Event Simulation as the underlying mechanism. However, these concepts and tools are inherently difficult to master and apply and often an excess in case implementers simply want to parallelise their own, custom agent-based model implementation. However, with the established programming languages in the field, Python, Java and C++, it is not easy to address the complexities of parallel programming due to unrestricted side effects and the intricacies of low-level locking semantics. Therefore, in this paper we propose the use of a lock-free approach to parallel ABS using Software Transactional Memory (STM) in conjunction with the pure functional programming language Haskell, which in combination, removes some of the problems and complexities of parallel implementations in imperative approaches. We present two case studies, in which we compare the performance of lock-based and lock-free STM implementations in two different well known Agent-Based Models, where we investigate both the scaling performance under increasing number of CPU cores and the scaling performance under increasing number of agents. We show that the lock-free STM implementations consistently outperform the lock-based ones and scale much better to increasing number of CPU cores both on local hardware and on Amazon EC. Further, by utilizing the pure functional language Haskell we gain the benefits of immutable data and lack of unrestricted side effects guaranteed at compile-time, making validation easier and leading to increased confidence in the correctness of an implementation, something of fundamental importance and benefit in parallel programming in general and scientific computing like ABS in particular. [ABSTRACT FROM AUTHOR]
- Published
- 2019
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22. Transactional Memory
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Shavit, Nir, Matveev, Alexander, and Kao, Ming-Yang, editor
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- 2016
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23. Preserving Access to Previous System States in the Lively Kernel
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Thamsen, Lauritz, Steinert, Bastian, Hirschfeld, Robert, Meinel, Christoph, Series editor, Leifer, Larry, Series editor, and Plattner, Hasso, editor
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- 2016
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24. Hyrise-NV: Instant Recovery for In-Memory Databases Using Non-Volatile Memory
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Schwalb, David, B.K., Girish Kumar, Dreseler, Markus, S., Anusha, Faust, Martin, Hohl, Adolf, Berning, Tim, Makkar, Gaurav, Plattner, Hasso, Deshmukh, Parag, Hutchison, David, Series editor, Kanade, Takeo, Series editor, Kittler, Josef, Series editor, Kleinberg, Jon M., Series editor, Mattern, Friedemann, Series editor, Mitchell, John C., Series editor, Naor, Moni, Series editor, Pandu Rangan, C., Series editor, Steffen, Bernhard, Series editor, Terzopoulos, Demetri, Series editor, Tygar, Doug, Series editor, Weikum, Gerhard, Series editor, Navathe, Shamkant B., editor, Wu, Weili, editor, Shekhar, Shashi, editor, Du, Xiaoyong, editor, Wang, Sean X., editor, and Xiong, Hui, editor
- Published
- 2016
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25. A Type System for Counting Logs of Multi-threaded Nested Transactional Programs
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Truong, Anh-Hoang, Van Hung, Dang, Dang, Duc-Hanh, Vu, Xuan-Tung, Hutchison, David, Series editor, Kanade, Takeo, Series editor, Kittler, Josef, Series editor, Kleinberg, Jon M., Series editor, Mattern, Friedemann, Series editor, Mitchell, John C., Series editor, Naor, Moni, Series editor, Pandu Rangan, C., Series editor, Steffen, Bernhard, Series editor, Terzopoulos, Demetri, Series editor, Tygar, Doug, Series editor, Weikum, Gerhard, Series editor, Bjørner, Nikolaj, editor, Prasad, Sanjiva, editor, and Parida, Laxmi, editor
- Published
- 2016
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26. Hybrid Transactional Memory Revisited
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Ruan, Wenjia, Spear, Michael, Hutchison, David, Series editor, Kanade, Takeo, Series editor, Kittler, Josef, Series editor, Kleinberg, Jon M., Series editor, Mattern, Friedemann, Series editor, Mitchell, John C., Series editor, Naor, Moni, Series editor, Pandu Rangan, C., Series editor, Steffen, Bernhard, Series editor, Terzopoulos, Demetri, Series editor, Tygar, Doug, Series editor, Weikum, Gerhard, Series editor, and Moses, Yoram, editor
- Published
- 2015
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27. Inherent Limitations of Hybrid Transactional Memory
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Alistarh, Dan, Kopinsky, Justin, Kuznetsov, Petr, Ravi, Srivatsan, Shavit, Nir, Hutchison, David, Series editor, Kanade, Takeo, Series editor, Kittler, Josef, Series editor, Kleinberg, Jon M., Series editor, Mattern, Friedemann, Series editor, Mitchell, John C., Series editor, Naor, Moni, Series editor, Pandu Rangan, C., Series editor, Steffen, Bernhard, Series editor, Terzopoulos, Demetri, Series editor, Tygar, Doug, Series editor, Weikum, Gerhard, Series editor, and Moses, Yoram, editor
- Published
- 2015
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28. Automatic Optimization of Software Transactional Memory Through Linear Regression and Decision Tree
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Xiao, Yang, Li, Zhen, Atoofian, Ehsan, Jannesari, Ali, Hutchison, David, Series editor, Kanade, Takeo, Series editor, Kittler, Josef, Series editor, Kleinberg, Jon M., Series editor, Mattern, Friedemann, Series editor, Mitchell, John C., Series editor, Naor, Moni, Series editor, Pandu Rangan, C., Series editor, Steffen, Bernhard, Series editor, Terzopoulos, Demetri, Series editor, Tygar, Doug, Series editor, Weikum, Gerhard, Series editor, Wang, Guojun, editor, Zomaya, Albert, editor, Martinez, Gregorio, editor, and Li, Kenli, editor
- Published
- 2015
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29. Self-tuning in Distributed Transactional Memory
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Couceiro, Maria, Didona, Diego, Rodrigues, Luís, Romano, Paolo, Hutchison, David, Series editor, Kanade, Takeo, Series editor, Kittler, Josef, Series editor, Kleinberg, Jon M., Series editor, Kobsa, Alfred, Series editor, Mattern, Friedemann, Series editor, Mitchell, John C., Series editor, Naor, Moni, Series editor, Nierstrasz, Oscar, Series editor, Pandu Rangan, C., Series editor, Steffen, Bernhard, Series editor, Terzopoulos, Demetri, Series editor, Tygar, Doug, Series editor, Weikum, Gerhard, Series editor, Guerraoui, Rachid, editor, and Romano, Paolo, editor
- Published
- 2015
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30. Proactive Contention Avoidance
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Avni, Hillel, Dolev, Shlomi, Kosmas, Eleftherios, Hutchison, David, Series editor, Kanade, Takeo, Series editor, Kittler, Josef, Series editor, Kleinberg, Jon M., Series editor, Kobsa, Alfred, Series editor, Mattern, Friedemann, Series editor, Mitchell, John C., Series editor, Naor, Moni, Series editor, Nierstrasz, Oscar, Series editor, Pandu Rangan, C., Series editor, Steffen, Bernhard, Series editor, Terzopoulos, Demetri, Series editor, Tygar, Doug, Series editor, Weikum, Gerhard, Series editor, Guerraoui, Rachid, editor, and Romano, Paolo, editor
- Published
- 2015
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31. Nested Parallelism in Transactional Memory
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Filipe, Ricardo, Barreto, João, Hutchison, David, Series editor, Kanade, Takeo, Series editor, Kittler, Josef, Series editor, Kleinberg, Jon M., Series editor, Kobsa, Alfred, Series editor, Mattern, Friedemann, Series editor, Mitchell, John C., Series editor, Naor, Moni, Series editor, Nierstrasz, Oscar, Series editor, Pandu Rangan, C., Series editor, Steffen, Bernhard, Series editor, Terzopoulos, Demetri, Series editor, Tygar, Doug, Series editor, Weikum, Gerhard, Series editor, Guerraoui, Rachid, editor, and Romano, Paolo, editor
- Published
- 2015
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32. Algorithmic Techniques in STM Design
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Fatourou, Panagiota, Iaremko, Mykhailo, Kanellou, Eleni, Kosmas, Eleftherios, Hutchison, David, Series editor, Kanade, Takeo, Series editor, Kittler, Josef, Series editor, Kleinberg, Jon M., Series editor, Kobsa, Alfred, Series editor, Mattern, Friedemann, Series editor, Mitchell, John C., Series editor, Naor, Moni, Series editor, Nierstrasz, Oscar, Series editor, Pandu Rangan, C., Series editor, Steffen, Bernhard, Series editor, Terzopoulos, Demetri, Series editor, Tygar, Doug, Series editor, Weikum, Gerhard, Series editor, Guerraoui, Rachid, editor, and Romano, Paolo, editor
- Published
- 2015
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33. Framework Support for the Efficient Implementation of Multi-version Algorithms
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Dias, Ricardo J., Vale, Tiago M., Lourenço, João M., Hutchison, David, Series editor, Kanade, Takeo, Series editor, Kittler, Josef, Series editor, Kleinberg, Jon M., Series editor, Kobsa, Alfred, Series editor, Mattern, Friedemann, Series editor, Mitchell, John C., Series editor, Naor, Moni, Series editor, Nierstrasz, Oscar, Series editor, Pandu Rangan, C., Series editor, Steffen, Bernhard, Series editor, Terzopoulos, Demetri, Series editor, Tygar, Doug, Series editor, Weikum, Gerhard, Series editor, Guerraoui, Rachid, editor, and Romano, Paolo, editor
- Published
- 2015
- Full Text
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34. Disjoint-Access Parallelism in Software Transactional Memory
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Attiya, Hagit, Fatourou, Panagiota, Hutchison, David, Series editor, Kanade, Takeo, Series editor, Kittler, Josef, Series editor, Kleinberg, Jon M., Series editor, Kobsa, Alfred, Series editor, Mattern, Friedemann, Series editor, Mitchell, John C., Series editor, Naor, Moni, Series editor, Nierstrasz, Oscar, Series editor, Pandu Rangan, C., Series editor, Steffen, Bernhard, Series editor, Terzopoulos, Demetri, Series editor, Tygar, Doug, Series editor, Weikum, Gerhard, Series editor, Guerraoui, Rachid, editor, and Romano, Paolo, editor
- Published
- 2015
- Full Text
- View/download PDF
35. Design and implementation of a fully transparent partial abort support for software transactional memory
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Alessandro Pellegrini, Pierangelo Di Sanzo, Andrea Piccione, Francesco Quaglia, Pellegrini, A, Di Sanzo, P, Piccione, A, and Quaglia, F
- Subjects
partial abort ,software transactional memory ,static binary instrumentation ,transactional memory ,Settore ING-INF/05 ,Software - Abstract
Software transactional memory (STM) provides synchronization support to ensure atomicity and isolation when threads access shared data in concurrent applications. With STM, shared data accesses are encapsulated within transactions automatically handled by the STM layer. Hence, programmers are not requested to use code-synchronization mechanisms explicitly, like locking. In this article, we present our experience in designing and implementing a partial abort scheme for STM. The objective of our work is threefold: (1) enabling STM to undo only part of the transaction execution in the case of conflict, (2) designing a scheme that is fully transparent to programmers, thus also allowing to run existing STM applications without modifications, and (3) providing a scheme that can be easily integrated within existing STM runtime environments without altering their internal structure. The scheme we designed is based on automated software instrumentation, which injects into the application capabilities to undo the required portions of transaction executions. Further, it can correctly undo also non-transactional operations executed on the stack and the heap during a transaction. This capability allows programmers to write transactional code without concerns about the side effects of aborted transactions on both shared and thread-private data. We integrated and evaluated our partial abort scheme within the TinySTM open-source library. We analyze the experimental results we achieved with common STM benchmark applications, focusing on the advantages and disadvantages of the proposed solutions for implementing our scheme's different components. Hence, we highlight the appropriate choices and possible solutions to improve partial abort schemes further.
- Published
- 2022
36. Decomposing Opacity
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Lesani, Mohsen, Palsberg, Jens, Hutchison, David, Series editor, Kanade, Takeo, Series editor, Kittler, Josef, Series editor, Kleinberg, Jon M., Series editor, Kobsa, Alfred, Series editor, Mattern, Friedemann, Series editor, Mitchell, John C., Series editor, Naor, Moni, Series editor, Nierstrasz, Oscar, Series editor, Pandu Rangan, C., Series editor, Steffen, Bernhard, Series editor, Terzopoulos, Demetri, Series editor, Tygar, Doug, Series editor, Weikum, Gerhard, Series editor, and Kuhn, Fabian, editor
- Published
- 2014
- Full Text
- View/download PDF
37. Reusable Concurrent Data Types
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Gramoli, Vincent, Guerraoui, Rachid, Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Kobsa, Alfred, editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Terzopoulos, Demetri, editor, Tygar, Doug, editor, Weikum, Gerhard, editor, and Jones, Richard, editor
- Published
- 2014
- Full Text
- View/download PDF
38. HiperTM: High Performance, Fault-Tolerant Transactional Memory
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Hirve, Sachin, Palmieri, Roberto, Ravindran, Binoy, Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Doug, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Chatterjee, Mainak, editor, Cao, Jian-nong, editor, Kothapalli, Kishore, editor, and Rajsbaum, Sergio, editor
- Published
- 2014
- Full Text
- View/download PDF
39. On Developing Optimistic Transactional Lazy Set
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Hassan, Ahmed, Palmieri, Roberto, Ravindran, Binoy, Hutchison, David, Series editor, Kanade, Takeo, Series editor, Kittler, Josef, Series editor, Kleinberg, Jon M., Series editor, Kobsa, Alfred, Series editor, Mattern, Friedemann, Series editor, Mitchell, John C., Series editor, Naor, Moni, Series editor, Nierstrasz, Oscar, Series editor, Pandu Rangan, C., Series editor, Steffen, Bernhard, Series editor, Terzopoulos, Demetri, Series editor, Tygar, Doug, Series editor, Weikum, Gerhard, Series editor, Aguilera, Marcos K., editor, Querzoni, Leonardo, editor, and Shapiro, Marc, editor
- Published
- 2014
- Full Text
- View/download PDF
40. WFR-TM: Wait-Free Readers without Sacrificing Speculation of Writers
- Author
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Fatourou, Panagiota, Kanellou, Eleni, Kosmas, Eleftherios, Rabbi, Md Forhad, Hutchison, David, Series editor, Kanade, Takeo, Series editor, Kittler, Josef, Series editor, Kleinberg, Jon M., Series editor, Kobsa, Alfred, Series editor, Mattern, Friedemann, Series editor, Mitchell, John C., Series editor, Naor, Moni, Series editor, Nierstrasz, Oscar, Series editor, Pandu Rangan, C., Series editor, Steffen, Bernhard, Series editor, Terzopoulos, Demetri, Series editor, Tygar, Doug, Series editor, Weikum, Gerhard, Series editor, Aguilera, Marcos K., editor, Querzoni, Leonardo, editor, and Shapiro, Marc, editor
- Published
- 2014
- Full Text
- View/download PDF
41. Automatic Tuning of the Parallelism Degree in Hardware Transactional Memory
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Rughetti, Diego, Romano, Paolo, Quaglia, Francesco, Ciciani, Bruno, Hutchison, David, Series editor, Kanade, Takeo, Series editor, Kittler, Josef, Series editor, Kleinberg, Jon M., Series editor, Kobsa, Alfred, Series editor, Mattern, Friedemann, Series editor, Mitchell, John C., Series editor, Naor, Moni, Series editor, Nierstrasz, Oscar, Series editor, Pandu Rangan, C., Series editor, Steffen, Bernhard, Series editor, Terzopoulos, Demetri, Series editor, Tygar, Doug, Series editor, Weikum, Gerhard, Series editor, Silva, Fernando, editor, Dutra, Inês, editor, and Santos Costa, Vítor, editor
- Published
- 2014
- Full Text
- View/download PDF
42. ProPS: A Progressively Pessimistic Scheduler for Software Transactional Memory
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Rito, Hugo, Cachopo, João, Hutchison, David, Series editor, Kanade, Takeo, Series editor, Kittler, Josef, Series editor, Kleinberg, Jon M., Series editor, Kobsa, Alfred, Series editor, Mattern, Friedemann, Series editor, Mitchell, John C., Series editor, Naor, Moni, Series editor, Nierstrasz, Oscar, Series editor, Pandu Rangan, C., Series editor, Steffen, Bernhard, Series editor, Terzopoulos, Demetri, Series editor, Tygar, Doug, Series editor, Weikum, Gerhard, Series editor, Silva, Fernando, editor, Dutra, Inês, editor, and Santos Costa, Vítor, editor
- Published
- 2014
- Full Text
- View/download PDF
43. Non-preemptive Scheduling of Real-Time Software Transactional Memory
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Barros, António, Pinho, Luís Miguel, Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Doug, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Maehle, Erik, editor, Römer, Kay, editor, Karl, Wolfgang, editor, and Tovar, Eduardo, editor
- Published
- 2014
- Full Text
- View/download PDF
44. Comparing the performance of concurrent hash tables implemented in Haskell.
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Duarte, Rodrigo Medeiros, Du Bois, André Rauber, Pilla, Maurício Lima, Cavalheiro, Gerson Geraldo H., and Reiser, Renata Hax Sander
- Subjects
- *
HASKELL (Computer program language) , *SYNCHRONIZATION , *COMPUTER programming , *COMPUTER algorithms , *COMPUTER systems - Abstract
Abstract This paper presents seven concurrent hash table implementations in Haskell, ranging from low-level synchronization mechanisms to high-level ones such as transactional memories. The hash tables were compared using different initial sizes, load factors, data types and hash functions. We also present a case study on implementing a color palette algorithm using the hash tables. The result of the comparison between the algorithms shows that the implementation using the STM Haskell transactional memory library and fine-grain synchronization provides the best performance and good scalability, followed by the implementation using lock striping and MVars. Highlights • The paper describes seven concurrent hash table implementations in Haskell. • Different abstractions were used: MVars, compare and swap, and transactional memory. • Detailed performance comparison of the hash tables is presented. • STM Haskell with fine-grain synchronization shows the best performance in overall. [ABSTRACT FROM AUTHOR]
- Published
- 2019
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45. Software Transactional Memory
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Fraser, Keir, Vossen, Gottfried, Section Editor, Liu, Ling, editor, and Özsu, M. Tamer, editor
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- 2018
- Full Text
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46. Proving Opacity of Transactional Memory with Early Release
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Siek Konrad and Wojciechowski Paweł T.
- Subjects
concurrency ,parallel programming ,software transactional memory ,safety ,early release ,Electronic computers. Computer science ,QA75.5-76.95 - Abstract
Transactional Memory (TM) is an alternative way of synchronizing concurrent accesses to shared memory by adopting the abstraction of transactions in place of low-level mechanisms like locks and barriers. TMs usually apply optimistic concurrency control to provide a universal and easy-to-use method of maintaining correctness. However, this approach performs a high number of aborts in high contention workloads, which can adversely affect performance. Optimistic TMs can cause problems when transactions contain irrevocable operations. Hence, pessimistic TMs were proposed to solve some of these problems. However, an important way of achieving efficiency in pessimistic TMs is to use early release. On the other hand, early release is seemingly at odds with opacity, the gold standard of TM safety properties, which does not allow transactions to make their state visible until they commit. In this paper we propose a proof technique that makes it possible to demonstrate that a TM with early release can be opaque as long as it prevents inconsistent views.
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- 2015
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47. Proving Non-opacity
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Lesani, Mohsen, Palsberg, Jens, Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Doug, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, and Afek, Yehuda, editor
- Published
- 2013
- Full Text
- View/download PDF
48. Exploiting Locality in Lease-Based Replicated Transactional Memory via Task Migration
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Hendler, Danny, Naiman, Alex, Peluso, Sebastiano, Quaglia, Francesco, Romano, Paolo, Suissa, Adi, Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Doug, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, and Afek, Yehuda, editor
- Published
- 2013
- Full Text
- View/download PDF
49. Generic Multiversion STM
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Lu, Li, Scott, Michael L., Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Doug, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, and Afek, Yehuda, editor
- Published
- 2013
- Full Text
- View/download PDF
50. Access Annotation for Safe Program Parallelization
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Ding, Chen, Liu, Lei, Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Doug, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Hsu, Ching-Hsien, editor, Li, Xiaoming, editor, Shi, Xuanhua, editor, and Zheng, Ran, editor
- Published
- 2013
- Full Text
- View/download PDF
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