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2 results on '"split-capacitor bias control technique"'

1. A 66-dB SNDR Pipelined Split-ADC in 40-nm CMOS Using a Class-AB Residue Amplifier.

Author

Akter, Md Shakil, Sehgal, Rohan, van der Goes, Frank, Makinwa, Kofi A. A., and Bult, Klaas

Subjects
TRANSISTOR amplifiers, ANALOG-to-digital converters, CALIBRATION
Abstract

This paper presents a closed-loop class-AB residue amplifier for pipelined analog-to-digital converters (ADCs). It consists of a push–pull structure with a “split-capacitor” biasing circuit that enhances its power efficiency. The amplifier is inherently quite linear, and so incomplete settling can be used to save power while still maintaining sufficient linearity. This also allows the amplifier’s gain to be corrected by adjusting its bias current. When combined with digital gain-error detection, in this case the split-ADC technique, the result is a power-efficient gain calibration scheme. In a prototype pipelined ADC, this scheme converges in only 12 000 clock cycles. With a near-Nyquist input, the ADC achieves 66-dB SNDR and 77.3-dB SFDR at 53 MS/s. Implemented in 40-nm CMOS, it dissipates 9 mW, of which 0.83 mW is consumed in the residue amplifiers. This represents a 1.8 $\times $ improvement in power efficiency compared to state-of-the-art class-AB residue amplifiers. [ABSTRACT FROM AUTHOR]

Published
2018
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2. A 66-dB SNDR Pipelined Split-ADC in 40-nm CMOS Using a Class-AB Residue Amplifier

Author

Kofi A. A. Makinwa, Klaas Bult, Rohan Sehgal, Shakil Akter, and Frank van der Goes

Subjects
Power dissipation, Spurious-free dynamic range, Computer science, Capacitance, Capacitors, class-AB residue amplifier, 02 engineering and technology, Transistors, differential sampling, law.invention, analog-to-digital conversion, Linearity, split-capacitor bias control technique, law, Hardware_INTEGRATEDCIRCUITS, 0202 electrical engineering, electronic engineering, information engineering, Electronic engineering, Hardware_ARITHMETICANDLOGICSTRUCTURES, Electrical and Electronic Engineering, Clocks, Amplifier, 020208 electrical & electronic engineering, Transistor, Biasing, Analog gain correction, Capacitor, CMOS, Calibration, split-ADC calibration, Electrical efficiency, incomplete settling
Abstract

This paper presents a closed-loop class-AB residue amplifier for pipelined analog-to-digital converters (ADCs). It consists of a push–pull structure with a “split-capacitor” biasing circuit that enhances its power efficiency. The amplifier is inherently quite linear, and so incomplete settling can be used to save power while still maintaining sufficient linearity. This also allows the amplifier’s gain to be corrected by adjusting its bias current. When combined with digital gain-error detection, in this case the split-ADC technique, the result is a power-efficient gain calibration scheme. In a prototype pipelined ADC, this scheme converges in only 12 000 clock cycles. With a near-Nyquist input, the ADC achieves 66-dB SNDR and 77.3-dB SFDR at 53 MS/s. Implemented in 40-nm CMOS, it dissipates 9 mW, of which 0.83 mW is consumed in the residue amplifiers. This represents a 1.8 $\times $ improvement in power efficiency compared to state-of-the-art class-AB residue amplifiers.

Published
2018
Full Text
View/download PDF

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