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Sn-doped indium oxide (ITO) semiconductor nano-films are fabricated by plasma-enhanced atomic layer deposition using trimethylindium (TMIn), tetrakis(dimethylamino)tin (TDMASn), and O2 plasma as the sources of In, Sn and O, respectively. A shared temperature window of 150 °C– 200 °C is observed for the deposition of ITO nano-films. The introduction of Sn into indium oxide is found to increase the concentration of oxygen into the ITO films and inhibit crystallization. Furthermore, two oxidation states are observed for In and Sn, respectively. With the increment of interfaces of In–O/Sn–O in the ITO films, the relative percentage of In3+ ions increases and that of Sn4+ decreases, which is generated by interfacial competing reactions. By optimizing the channel component, the In0.77Sn0.23O1.11 thin-film transistors (TFTs) demonstrate high performance, including μ FE of 52.7 cm2 V−1 s−1, and a high I ON/ I OFF of ∼5 × 109. Moreover, the devices show excellent positive bias temperature stress stability at 3 MV cm−1 and 85 °C, i.e. a minimal V th shift of 0.017 V after 4 ks stress. This work highlights the successful application of ITO semiconductor nano-films by ALD for TFTs. [ABSTRACT FROM AUTHOR]

Many low‐power technologies have been developed for high‐performance displays. One method is to vary the refresh rate according to the input image, where frequencies are reduced over still images and slow‐moving videos. To support the variable refresh rate scheme, the programmable gate driver circuit should be integrated. This paper proposes a thin‐film transistor (TFT) shift register of which output pulse is simply controlled by an enable signal. Because the output pulse generation is directly adjusted without the previous programming period, various output pulse sequences are possible with the high flexibility. The shift register is composed by adding six TFTs and one capacitor to a conventional circuit that provides a carry pulse to a next stage. The simulation program with integrated circuit emphasis (SPICE) simulation ensures that gate pulses for any numbers of lines in any regions can be generated within one frame only by applying the enable signal at the corresponding timing, resulting in multiple refresh frequencies in a screen. In addition, it is verified that additional TFTs and capacitor contribute to only the negligible increase in power consumption by 2.1%, compared to a conventional shift register. [ABSTRACT FROM AUTHOR]

We proposed a novel measurement method and system to measure the electrical characteristics of non-patterned semiconductor films to estimate the final device’s properties. The proposed method is based on measuring bottom-gate structure thin-film transistor (TFT) using the probe pins as source and drain electrodes. We carefully designed the array structure and material of the probe pin to effectively detect extremely low-level currents without patterned electrodes on the semiconductor film. The contact pressure was also carefully controlled through continuous monitoring using an implemented pressure sensor to ensure the reliability and reproducibility of the measured data. In addition, we developed a method of extracting device parameters, such as the threshold voltage and field-effect mobility, from the measured data, considering the geometric factor of the proposed method. Comparative analysis between the measurement results of the film sample using the proposed system and that of the final TFT sample exhibited similar results with slight deviations. Furthermore, the proposed system provided similar results under repetitive measurements. Consequently, the proposed method and system successfully demonstrated the estimation of the final TFT’s properties by measuring the electrical characteristics of the non-patterned semiconductor film with excellent reliability, highlighting the possibility of effectively reducing costs for development and fabrication.

In this paper, we delve into recent advancements in the fabrication of high-performance n-type oxide semiconductor thin-film transistors (TFTs) through crystallization pathways. The last two decades have seen a rapid proliferation of applications employing amorphous oxide semiconductor (AOS) transistors, from display technologies to semiconductor chips. However, with the growing demand for ultra-high-resolution organic light-emitting diodes, flexible electronics, and next-generation electronic devices, interest in oxide semiconductors exhibiting high mobility and exceptional reliability has grown. However, AOS TFTs must balance the competing demands of mobility and stability. Here, we explore various crystallization methods of enhancing the device performance of oxide semiconductors, alongside the intrinsic challenges associated with crystalline oxide semiconductors. Our discussion highlights the potential solutions presented by controlling crystalline quality in terms of grain size and orientation. We propose that advanced manufacturing techniques coupled with a profound understanding of materials science are needed to effectively address these issues. [ABSTRACT FROM AUTHOR]

Low‐power electronic devices are of increasing interest with high‐k gate insulators (GI). Herein, the performance and stability of low‐temperature poly‐Si (LTPS) thin‐film transistors (TFTs) are investigated with two different GIs: spray pyrolyzed zirconiumaluminum oxide (ZAO) directly deposited on poly‐Si, and SiO2/ZAO stack GI. The LTPS TFT with SiO2/ZAO stack GI exhibits hysteresis free characteristics with a threshold voltage of −0.2 V, field‐effect mobility of 114.4 cm2 V−1 s−1, subthreshold swing of 0.10 V dec−1, and high on/off current ratio of 7.3 × 108, at a gate voltage sweeping ±6 V. The TFT exhibits very stable operation under negative bias temperature stress. The X‐ray photoelectron spectroscopy and high‐resolution transmission electron microscopy analyses demonstrate that the diffusion of Zr and Al into poly‐Si deteriorates device performance with ZAO only GI. A thin SiO2 on LTPS blocks the diffusion of Zr and Al, resulting the high‐performance and stable p‐type LTPS TFT with a high‐k SiO2/ZAO stack GI. Finally, a 7‐stage ring oscillator using LTPS TFTs with SiO2/ZAO stack GI is demonstrated, exhibiting an oscillation frequency of 7.49 MHz and a propagation delay of 9.54 ns at a supply voltage of 6 V, indicating its suitability for low‐power consumption TFT electronics and displays. [ABSTRACT FROM AUTHOR]

With the continuous expansion of pixel arrays in digital microfluidics (DMF) chips, precise droplet control has emerged as a critical issue requiring detailed consideration. This paper proposes a novel capacitance-based droplet sensing system for thin-film transistor DMF. The proposed circuit features a distinctive inner and outer dual-pixel electrode structure, integrating droplet driving and sensing functionalities. Discharge occurs exclusively at the inner electrode during droplet sensing, effectively addressing droplet perturbation in existing sensing circuits. The circuit employs a novel fan-shaped structure of thin-film transistors. Simulation results show that it can provide a 48 V pixel voltage and demonstrate a sensing voltage difference of over 10 V between deionized water and silicone oil, illustrating its proficiency in droplet driving and accurate sensing. The stability of threshold voltage drift and temperature was also verified for the circuit. The design is tailored for integration into active matrix electrowetting-on-dielectric (AM-EWOD) chips, offering a novel approach to achieve precise closed-loop control of droplets. [ABSTRACT FROM AUTHOR]

Capacitorless two‐transistor (2T0C) dynamic random‐access memory (DRAM) cells comprising oxide thin‐film transistors (TFTs) show potential as low‐power and high‐density DRAM cells; however, the multiply–accumulate (MAC) operation using these cells is not yet realized. In this study, 2T0C DRAM cells comprising amorphous indium–tin–gallium–zinc oxide TFTs are fabricated for MAC operations. In a 2T0C DRAM cell, one transistor acts as a write transistor and the other as a read transistor, whose gate capacitance corresponds to the data storage capacitance. The cells have a long retention time of 1000 s, which is 104 times longer than that of conventional DRAM cells, owing to the extremely low leakage current of the TFTs (1.11 × 10−18 A µm−1). These cells satisfy the original condition for synaptic devices, in which a proportional relationship exists between the input and output. The MAC operation is performed using two cells. This study demonstrates the usefulness of oxide TFTs in artificial neural networks. [ABSTRACT FROM AUTHOR]

Monolithic three‐dimensional (M3D) integration advances integrated circuits by enhancing density and energy efficiency. Ferroelectric thin‐film transistors (Fe‐TFTs) attract attention for neuromorphic computing and back‐end‐of‐the‐line (BEOL) compatibility. However, M3D faces challenges like increased runtime temperatures due to limited heat dissipation, impacting system reliability. This work demonstrates the effect of temperature impact on single‐gate (SG) Fe‐TFT reliability. SG Fe‐TFTs have limitations such as read‐disturbance and small memory windows, constraining their use. To mitigate these, dual‐gate (DG) Fe‐TFTs are modeled using technology computer‐aided design, comparing their performance. Compute‐in‐memory (CIM) architectures with SG and DG Fe‐TFTs are investigated for deep neural networks (DNN) accelerators, revealing heat's detrimental effect on reliability and inference accuracy. DG Fe‐TFTs exhibit about 4.6x higher throughput than SG Fe‐TFTs. Additionally, thermal effects within the simulated M3D architecture are analyzed, noting reduced DNN accuracy to 81.11% and 67.85% for SG and DG Fe‐TFTs, respectively. Furthermore, various cooling methods and their impact on CIM system temperature are demonstrated, offering insights for efficient thermal management strategies. [ABSTRACT FROM AUTHOR]

A c-axis aligned crystalline indium gallium zinc oxide (CAAC-IGZO) possesses unique properties beneficial for thin-film transistors (TFTs). In this study, we investigate the effect of oxygen ratio and radio frequency (RF) power on the structural, electrical, and operational characteristics of CAAC-IGZO thin films. Films were deposited on SiO2 substrates using an RF sputtering system equipped with a target containing In, Ga, Zn, and O with a composition ratio of 1:1:1:4. The effect of oxygen percentage on the structural characteristics was analyzed by X-ray diffraction (XRD), transmission electron microscopy (TEM). The oxygen percentage in the film was found to play a crucial role in forming the CAAC-IGZO and orientation of the thin films. With increasing O2 fraction, the (009)-preferred orientation of the films improved. X-ray absorption spectroscopy also validated the improved orientations of the CAAC-IGZO with high O2 concentrations up to 70%. In terms of TFT performance, however, the device with 3.3% oxygen exhibited the best performance with a saturation mobility of 10.9 cm2 V− 1 s− 1. TFT devices were prepared at a low oxygen fraction (10%) with different RF power inputs from 100 to 250 W, where the device prepared with highest power (250 W) showed the best performance. [ABSTRACT FROM AUTHOR]

Many advanced technologies have been employed in high-performance active matrix displays, including liquid crystal displays, organic light-emitting diode displays, and micro-light-emitting diode displays. On the other side, there exists a strong demand for cost reduction, and it is one of the low-cost schemes for integrating the driver circuit in a panel based on thin-film transistor technologies. This paper reviews the overall concept, operation principles, and various circuit approaches in shift registers for scanning pulse generation. In addition, it deals with the implementation of additional functionalities in gate drivers to support pixel compensation, multi-line driving, in-cell capacitive touch screen, pixel sensing, and adaptive scanning region control. [ABSTRACT FROM AUTHOR]

The thin film of indium gallium tin oxide (IGTO) was deposited by the RF magnetron sputtering system with different oxygen flow ratios, which controls the numbers of defects and free carriers to change the characteristics of thin-film transistors ((TFTs). We determined the subgap density-of-states (DOS) from the transfer characteristics curve by the unified subthreshold coupling factor technique to analyze the response of oxygen-related trap sites within the thin films fabricated under different oxygen flows. We used Python to fit the DOS data with a combination of two exponential forms, inferring that, during the increase in the oxygen flow ratio, acceptor-like oxygen-related trap sites can be gradually compensated. The IGTO TFTs exhibit optimized performance when subjected to annealing at 200 °C for 1 h with a 5% oxygen flow ratio, showing a threshold voltage (Vth) of 1.76 V, a field-effect mobility of 0.355 cm2/V s, an impressive on/off drain current ratio of 1.42 × 106, and a subthreshold swing (SS) of 0.665 V/decade. [ABSTRACT FROM AUTHOR]

The new AMOLED pixel circuit for high‐resolution applications such as AR/VR has been proposed. The simultaneous emission is adopted to minimize pixel elements. The proposed circuit can compensate for variations of threshold voltage and sub‐threshold voltage even composed with 3 TFTs and 1 capacitor. [ABSTRACT FROM AUTHOR]

A low‐temperature technology for fabricating thin‐film transistors (TFTs) is essential for the realization of electronic systems on flexible substrates. Presently reviewed are improved techniques for forming the source/drain regions and reducing the population of channel defects in a metal‐oxide TFT. These have been applied to the construction of different TFT structures, including ones with bottom gate, top gate, and dual gates. The utility of the improved 300‐°C technology has been demonstrated by the realization of a variety of electronic systems, such as a gate‐driver on array for active‐matrix displays, an analog front‐end for acquiring biopotential signals, and an artificial neural network for neuromorphic computing. [ABSTRACT FROM AUTHOR]

We introduce a new architecture, alternative double work function (a‐DWF), device to dramatically enhance the output current of source gated transistors (SGT) while retaining low voltage saturation. The smaller output current of SGT and previous DWF devices compared to conventional thin‐film transistors (TFT) has previously limited their application range. [ABSTRACT FROM AUTHOR]

We demonstrate the compensation of device‐to‐device variation in threshold voltage using programmable ferroelectric indium‐gallium‐zinc‐oxide thin‐film transistors. Furthermore, degradationinduced threshold voltage shift can be mitigated by programming, setting the characteristics back to their pristine state. This can be a promising alternative for the replacement of complex VT compensation circuits in display applications. [ABSTRACT FROM AUTHOR]

CO2 monitoring is important for achieving net-zero emissions. Here, we report on a CO2 gas sensor based on an In2O3 thin-film transistor (TFT), which is expected to realize both low-temperature operation and high sensitivity. The effect of channel thickness on TFT performance is well known; however, its effect on CO2 sensitivity has not been fully investigated. We fabricated In2O3 TFTs of various thicknesses to evaluate the effect of channel thickness on CO2 sensitivity. Consequently, TFT gas sensors with thinner channels exhibited higher CO2 sensitivity. This is because the surface effect is more prominent for a thinner film, suggesting that charge transfer between gas molecules and the channel surface through gas adsorption has a significant impact on changes in the TFT parameters in the subthreshold region. The results showed that the In2O3 TFT in thin channels is a promising candidate for CO2-sensitive TFT gas sensors and is useful for understanding an effect of gas adsorption in oxide TFTs with a very thin channel as well. [ABSTRACT FROM AUTHOR]

Atomic-layer-deposited (ALD) zinc-tin-oxide (ZTO) thin films offer promising electronic properties for many applications, but their development has been limited by their tendency to experience significant nucleation delay—which tends to introduce impurity—during deposition. This study utilized in-situ quartz crystal microbalance (QCM) analysis combined with ex-situ compositional analysis to examine the nucleation-delay characteristics of ZTO ALD and their dependence upon the oxidant-precursor settings. The results indicated that nucleation delay occurred solely during the ZnO-on-SnO 2 deposition step as a result of persisting ethyl ligands of the organozinc precursor, diethylzinc, which could be mitigated by using H 2 O 2 instead of H 2 O as the oxidant precursor and introducing a discrete-feeding or exposure procedure for the H 2 O 2 half cycle to increase the effective oxidant dose. The effects of nucleation delay on the electronic properties of ALD ZTO films was examined with thin-film transistor (TFT) devices, where suppression of nucleation delay yielded substantial improvement in the device performance, achieving a high field-effect mobility of 21.5 cm2/V s, low sub-threshold swing of 0.16, high on/off ratio of 2 × 108, and enhance-mode operation without needing elevated-temperature post-processing. The findings present valuable improvements over the state of the art and provide insights useful for the development of other types of ALD multi-component films. [ABSTRACT FROM AUTHOR]

Ultra-thin ZnO thin-film transistors with a channel thickness of <10 nm have disadvantages of a high threshold voltage and a low carrier mobility due to a low carrier concentration. Although these issues can be addressed by utilizing the strong reducing power of tri-methyl-aluminum, a method is required to control parameters such as the threshold voltage. Therefore, we fabricated a ZnO/Al2O3 thin-film transistor with a thickness of 6 nm and adjusted the threshold voltage and carrier mobility through the modulation of carrier generation by varying the growth temperature of Al2O3. As the growth temperature of Al2O3 increased, oxygen vacancies generated at the hetero–oxide interface increased, supplying a free carrier into the channel and causing the threshold voltage to shift in the negative direction. The optimized device, a ZnO/Al2O3 thin-film transistor with a growth temperature of 140 °C, exhibited a μsat of 12.26 cm2/V∙s, Vth of 8.16 V, SS of 0.65 V/decade, and ION/OFF of 3.98 × 106. X-ray photoelectron spectroscopy was performed to analyze the properties of ZnO/Al2O3 thin films. [ABSTRACT FROM AUTHOR]

Copyright of Chinese Journal of Liquid Crystal & Displays is the property of Chinese Journal of Liquid Crystal & Displays and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

Flexible wearable electronics have been developing rapidly in recent years, and one of its core devices, thin‐film transistor (TFT), is also attracting attention. Current TFT preparation processes usually require high annealing temperatures (>350 °C), which is not conducive to their application on most flexible substrates (PET, PEN, nanopaper, etc.). In this article, a strategy for the room temperature preparation of Nd:AIZO/Al2O3 dual‐layer TFT devices is proposed, which has appreciable electrical properties without additional annealing treatment. Taguchi orthogonal experimental methods are used to investigate the effects of three essential process parameters on the performance of the films and devices. As Nd:AIZO deposition time decreases and Al2O3 oxygen percentage and time during deposition increase, the μsat and SS of TFT devices are improved. With the preferred combination of parameters applied to the device preparation, the device exhibits a saturation mobility μsat of 24.3 cm2 V−1 s−1, a threshold voltage Vth of −1.4 V, a subthreshold swing SS of 0.21 V decade−1 and an Ion/Ioff ratio of 4.26 × 108. The ultra‐thin Al2O3 layer act as defect modification and form high‐speed electron transport in channel layer. The room temperature preparation of the dual‐layer TFT process proposed in this article is compatible with large‐size low‐cost flexible substrates. It has great potential for application in green flexible wearable electronics. [ABSTRACT FROM AUTHOR]

In this work, the stability of hydrogenated amorphous silicon (a‐Si:H) thin‐film transistors (TFTs) under reliability (RA) test was studied and a two‐stage degradation behavior during the RA test was first observed. The influence of bandgap (Eg) of the SiNx gate insulator (GI) on the degradation behavior was studied and the SiNx GI of a high Eg was found of vital importance due to its better blocking capability against electron injection from gate electrode into GI. The results in this work indicated technological impact for a‐Si:H TFTs in high‐brightness LCD products for outdoor display applications. [ABSTRACT FROM AUTHOR]

This work evaluates the effect of self‐alignment on the performance of bottom‐gate IGZO TFTs for AMOLED backplanes via SPICE simulation. Transient simulations are used to evaluate the row and column scaling of self‐aligned and non‐self‐aligned IGZO TFT to make quantitative comparisons in terms of line, settle and discharge time. Essentially, this work addresses the following questions: (1) given that self‐aligned TFTs have lower mobility than non‐self‐aligned TFTs due to large differences in contact resistance, does the lower overlap capacitance of self‐aligned TFTs always lead to better transient performance than non‐self‐aligned TFTs? and (2) Under what condition(s) do non‐self‐aligned TFTs become comparable to self‐aligned TFTs in terms of transient performance? [ABSTRACT FROM AUTHOR]

Monolithic three‐dimensional (M3D) integration advances integrated circuits by enhancing density and energy efficiency. Ferroelectric thin‐film transistors (Fe‐TFTs) attract attention for neuromorphic computing and back‐end‐of‐the‐line (BEOL) compatibility. However, M3D faces challenges like increased runtime temperatures due to limited heat dissipation, impacting system reliability. This work demonstrates the effect of temperature impact on single‐gate (SG) Fe‐TFT reliability. SG Fe‐TFTs have limitations such as read‐disturbance and small memory windows, constraining their use. To mitigate these, dual‐gate (DG) Fe‐TFTs are modeled using technology computer‐aided design, comparing their performance. Compute‐in‐memory (CIM) architectures with SG and DG Fe‐TFTs are investigated for deep neural networks (DNN) accelerators, revealing heat's detrimental effect on reliability and inference accuracy. DG Fe‐TFTs exhibit about 4.6x higher throughput than SG Fe‐TFTs. Additionally, thermal effects within the simulated M3D architecture are analyzed, noting reduced DNN accuracy to 81.11% and 67.85% for SG and DG Fe‐TFTs, respectively. Furthermore, various cooling methods and their impact on CIM system temperature are demonstrated, offering insights for efficient thermal management strategies.

In this paper, we propose a bidirectional gate driver on array (GOA) circuit design based on indium gallium zinc oxide (IGZO) thin-film transistor (TFT) to support time-division driving method (TDDM) for in-cell touch displays. The proposed circuit allows the touch panel to pause the display for touch sensing operations to achieve a touch reporting rate as twice as the frame rate of a display. A dual low-level maintaining unit design is used to suppress influence of the threshold voltage shift of TFTs through alternately turning on the devices. Owing to recovery of threshold voltage shift under negative bias, this design can maintain stable performance during long time operation. A narrow border 6.5” in-cell LCD panel of 90 Hz display with a 180 Hz touch reporting rate is finally demonstrated.

We reported the fabrication of indium‐gallium‐zinc oxide (IGZO) thin‐film transistors (TFTs) by plasma‐enhanced atomic‐layer‐deposition (PEALD) process using different surface reactivities of the precursor‐substrate combinations with controlled deposition sequences. In‐Zn‐Ga (Case II) exhibited favorable subthreshold swing (SS) values of 313 mV/decade, and moderate mobility (µFE) of 29.3 cm2/Vs compared to In‐Ga‐Zn (Case I) (84 mV/decade and 33.4 cm2/Vs). [ABSTRACT FROM AUTHOR]

In this work, we report a systematic investigation of low‐temperature polycrystalline silicon (LTPS)‐based driving backboard of electronic paper. Firstly, LTPS‐based thin film transistors (TFTs) with extremely low off‐state leakage current at a large gate‐source voltage (VGS) of 30 V were obtained through detailed explorations of low‐temperature polycrystalline silicon technology. Meanwhile, the high on‐state current of LTPS‐TFTs also meet the requirements of fast signal writing to the storage capacitor due to their extremely high field‐effect mobility (~100 cm2 /V*s), making it possible to fabricate TFT devices with relatively small width/length ratios (W/L) to minimize feed‐through to the full extent. [ABSTRACT FROM AUTHOR]

We proposed a CMOS LTPS TFT‐based integrated driver circuit to generate the control signals for micro light‐emitting diode pixel circuits. The proposed circuit enables to generation of five output signals by sharing core logic without capacitors. We verified that the output signals remain stable through the simulation. [ABSTRACT FROM AUTHOR]

Copyright of Chinese Journal of Liquid Crystal & Displays is the property of Chinese Journal of Liquid Crystal & Displays and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

To fabricate oxide thin-film transistors (TFTs) with high performance and excellent stability, preparing high-quality semiconductor films in the channel bulk region and minimizing the defect states in the gate dielectric/channel interfaces and back-channel regions is necessary. However, even if an oxide transistor is composed of the same semiconductor film, gate dielectric/channel interface, and back channel, its electrical performance and operational stability are significantly affected by the thickness of the oxide semiconductor. In this study, solution process-based nanometer-scale thickness engineering of InZnO semiconductors was easily performed via repeated solution coating and annealing. The thickness-controlled InZnO films were then applied as channel regions, which were fabricated with almost identical film quality, gate dielectric/channel interface, and back-channel conditions. However, excellent operational stability and electrical performance suitable for oxide TFT backplane was only achieved using an 8 nm thick InZnO film. In contrast, the ultrathin and thicker films exhibited electrical performances that were either very resistive (high positive VTh and low on-current) or excessively conductive (high negative VTh and high off-current). This investigation confirmed that the quality of semiconductor materials, solution process design, and structural parameters, including the dimensions of the channel layer, must be carefully designed to realize high-performance and high-stability oxide TFTs. [ABSTRACT FROM AUTHOR]

With the increase in electronic devices across various applications, there is rising demand for selective carrier control. The split-gate consists of a gate electrode divided into multiple parts, allowing for the independent biasing of electric fields within the device. This configuration enables the potential formation of both p- and n-channels by injecting holes and electrons owing to the presence of the two gate electrodes. Applying voltage to the split-gate allows for the control of the Fermi level and, consequently, the barrier height in the device. This facilitates band bending in unipolar transistors and allows ambipolar transistors to operate as if unipolar. Moreover, the split-gate serves as a revolutionary tool to modulate the contact resistance by controlling the barrier height. This approach enables the precise control of the device by biasing the partial electric field without limitations on materials, making it adaptable for various applications, as reported in various types of research. However, the gap length between gates can affect the injection of the electric field for the precise control of carriers. Hence, the design of the gap length is a critical element for the split-gate structure. The primary investigation in this review is the introduction of split-gate technology applied in various applications by using diverse materials, the methods for forming the split-gate in each device, and the operational mechanisms under applied voltage conditions. [ABSTRACT FROM AUTHOR]

The density of donor-like state distributions in solution-processed indium–zinc-oxide (IZO) thin-film transistors (TFTs) is thoroughly analyzed using photon energy irradiation. This study focuses on quantitatively calculating the distribution of density of states (DOS) in IZO semiconductors, with a specific emphasis on their variation with indium concentration. Two calculation methods, namely photoexcited charge collection spectroscopy (PECCS) and photocurrent-induced DOS spectroscopy (PIDS), are employed to estimate the density of the donor-like states. This dual approach not only ensures the accuracy of the findings but also provides a comprehensive perspective on the properties of semiconductors. The results reveal a consistent characteristic: the Recombination–Generation (R-G) center energy ET, a key aspect of the donor-like state, is acquired at approximately 3.26 eV, irrespective of the In concentration. This finding suggests that weak bonds and oxygen vacancies within the Zn-O bonding structure of IZO semiconductors act as the primary source of R-G centers, contributing to the donor-like state distribution. By highlighting this fundamental aspect of IZO semiconductors, this study enhances our understanding of their charge-transport mechanisms. Moreover, it offers valuable insight for addressing stability issues such as negative bias illumination stress, potentially leading to the improved performance and reliability of solution-processed IZO TFTs. The study contributes to the advancement of displays and technologies by presenting further innovations and applications for evaluating the fundamentals of semiconductors. [ABSTRACT FROM AUTHOR]

The zinc-tin-oxide (ZTO) thin-film transistor (TFT) is one of the most promising candidates for advanced display applications, though its popularity is limited by its performances. In this work, a heterojunction channel strategy was adopted to regulate the electron transport behaviors and the TFT performances by manipulating the concentration and the distribution of oxygen vacancies, and a reasonable physical model was proposed based on experimental and simulation results. It is difficult to mediate the contradiction between mobility and threshold voltage for the single channel. Via a heterojunction channel strategy, desirable TFT performances, with mobility of 12.5 cm2/Vs, threshold voltage of 1.2 V and Ion/Ioff of 3 × 109, are achieved when the oxygen-vacancy-enriched layer gets close to the gate insulator (GI). The enhanced performances can be mainly attributed to the formation of two-dimensional electron gas (2DEG), the insensitive potential barrier and the reasonable distribution of oxygen vacancy. On the contrary, when the oxygen-vacancy-enriched layer stays away from GI, all the main performances degenerate due to the vulnerable potential well. The findings may facilitate the development and application of heterojunction channels for improving the performances of electronic devices. [ABSTRACT FROM AUTHOR]

This article presents a design of a VCO‐based ADC based on n‐type metal oxide thin‐film transistor (TFT). The TFTs are fabricated on a glass substrate using Indium Zinc Oxide technology. The VCO‐based ADC consists of a VCO, a level shifter and a sampling circuit, while the VCO is composed of a charge‐discharge cell and an inverter chain. The ADC has a 1.464 mm 2 area, 0.89 mW power consumption, an output frequency range of 1.41 KHz/V tuning sensitivity, 1.8% maximum linear error and achieves a SNDR of 34.2 dB in the case of an input signal of 1.5 Hz and a sampling rate of 20 S/s. [ABSTRACT FROM AUTHOR]

This work develops self‐aligned top‐gate (SA‐TG) amorphous indium‐tin‐zinc oxide (ITZO) thin‐film transistors (TFT) with high‐k AlOx gate insulator based on oxygen‐plasma formed source/drain technique. The fabricated SA‐TG TFTs based on this technique demonstrate good electrical performance, such as source/drain resistivity of less than 0.005W cm, high field‐effect mobility of 35.2 cm 2 /Vs, and near‐zero turn‐on voltage. Additionally, the SA‐TG high‐k devices exhibiting short‐channel effects only when the channel length is scaled to ~0.8 μm and demonstrated strong stability when subjected to thermal and gate bias stress. [ABSTRACT FROM AUTHOR]

With the continuous expansion of pixel arrays in digital microfluidics (DMF) chips, precise droplet control has emerged as a critical issue requiring detailed consideration. This paper proposes a novel capacitance-based droplet sensing system for thin-film transistor DMF. The proposed circuit features a distinctive inner and outer dual-pixel electrode structure, integrating droplet driving and sensing functionalities. Discharge occurs exclusively at the inner electrode during droplet sensing, effectively addressing droplet perturbation in existing sensing circuits. The circuit employs a novel fan-shaped structure of thin-film transistors. Simulation results show that it can provide a 48 V pixel voltage and demonstrate a sensing voltage difference of over 10 V between deionized water and silicone oil, illustrating its proficiency in droplet driving and accurate sensing. The stability of threshold voltage drift and temperature was also verified for the circuit. The design is tailored for integration into active matrix electrowetting-on-dielectric (AM-EWOD) chips, offering a novel approach to achieve precise closed-loop control of droplets.

Many advanced technologies have been employed in high-performance active matrix displays, including liquid crystal displays, organic light-emitting diode displays, and micro-light-emitting diode displays. On the other side, there exists a strong demand for cost reduction, and it is one of the low-cost schemes for integrating the driver circuit in a panel based on thin-film transistor technologies. This paper reviews the overall concept, operation principles, and various circuit approaches in shift registers for scanning pulse generation. In addition, it deals with the implementation of additional functionalities in gate drivers to support pixel compensation, multi-line driving, in-cell capacitive touch screen, pixel sensing, and adaptive scanning region control.

This review aims to provide a technical roadmap and an overview of recent progress in the development of backplane thin film transistors (TFTs) for organic light-emitting diodes flat panel displays and next-generation flexible displays. In the introduction, we provide a general overview of the research trends for backplane TFTs. The main part describes the current technical level and prospects for amorphous metal oxide semiconducting, metal halide perovskites, and 2D transition metal dichalcogenides TFTs. The summary and prospects are provided in the conclusion section.

The detection of Hydrogen sulfide (H2S) gas at room temperature measurement has gained interest owing to its low-power consumption, high stability and reducing the risk of explosion within the sight of flammable gases. In this study, we present a novel low-cost and environmental-friendly approach in developing SnO2 and CuO nanoparticles (green approach) and their deployment in transistor (bi-layer approach) for the detection of hydrogen sulfide (H2S) vapors. The crystallite size of as-synthesized SnO2 and CuO NPs were revealed with aid of diffraction peaks which were found to be 14 nm and 19 nm respectively and the elemental composition with structural morphology (spherical) were determined by EDAX and Fe-SEM analysis respectively. The CuO nanoparticles interaction with the surface of SnO2 affirms a p-n junction formation with large electron-hole movements, while the interaction of H2S gas molecules on to the surface of CuO leads to the formation of CuS which awfully reduces electrical resistance enhancing the electrical conductivity and the sensor response. The high sensitivity of 1.86 μA/ppm and selectivity response of 89.46 % was achieved for the exposure of H2S analyte among other analytes exposed such as NO2, CO, C2H5OH and C3H8. The results demonstrate that sensor designed is potent for the use in industrial, environmental, and safety applications, contributing to the mitigation of H2S-related risks.

We studied the impact of NF3 plasma treatment on the HfO2 gate insulator of amorphous tin oxide (a-SnOx) thin-film transistors (TFTs). The plasma treatment was for 0, 10, or 30 s. The HfO2 insulator demonstrated a slightly higher breakdown voltage, whereas the capacitance value remained almost constant (~150 nF/cm2). The linear mobility slightly increased from ~30 to ~35 cm2/Vs when the treatment time increased from 0 to 10 s, whereas a 30 s-treated TFT demonstrated a decreased mobility of ~15 cm2/Vs. The subthreshold swing and the threshold voltage remained in the 100–120 mV/dec. range and near 0 V, respectively. The hysteresis dramatically decreased from ~0.5 V to 0 V when a 10 s treatment was applied, and the 10 s-treated TFT demonstrated the best stability under high current stress (HCS) of 100 μA. The analysis of the tin oxide thin film crystallinity and oxygen environment demonstrated that the a-SnOx remained amorphous, whereas more metal–oxygen bonds were formed with a 10 s NF3 plasma treatment. We also demonstrate that the density of states (DOS) significantly decreased in the 10 s-treated TFT compared to the other conditions. The stability under HCS was attributed to the HfO2/a-SnOx interface quality. [ABSTRACT FROM AUTHOR]

In this work, indium silicon oxide (ISO) thin-film transistors (TFT) were developed with molybdenum as the source and drain contact using sputtering and lithography techniques. The influence of channel length on the electrical properties of the ISO TFTs was studied by varying the channel length from ultra-short 5 µm to 100 µm. The highest mobility of 13.23 cm2/V s with an on/off ratio of 108 order was obtained for the ISO TFT post-annealed at 150°C with a channel length of 5 µm and width of 250 µm. In addition, the bias stress stability of the ISO TFT was measured. [ABSTRACT FROM AUTHOR]

A fully soluble and photo-crosslinkable gate dielectric (6 F-SPI-Cinnamoyl: 6 F-SPI-CM) was synthesized. First, hydroxyl group substituted polyimide (6 F-SPI-Hydroxyl: 6 F-SPI-OH) polymer was prepared using monomers, 5-(2,5-dioxytetrahydrofuryl)-3-methyl-3-cyclohexene-1,2-dicarboxylic anhydride (DOCDA) and 4,4'-(perfluoropropane-2,2-diyl)dianiline (6FHAB) through polycondensation reaction. And, then 6 F-SPI-OH was further reacted with cinnamoyl chloride to prepare a photo-crosslinkable 6 F-SPI-CM. The thin film of photo-crosslinked 6 F-SPI-CM (C-6F-SPI-CM) showed the extremely low leakage current density of <1.0 x10−11 A/cm2. In addition, 6 F-SPI-CM was easily patterned by selective UV-light exposure. A flexible pentacene thin-film transistor (TFT) on polyethersulfone (PES) substrate with photo-crosslinked 6 F-SPI-CM as a gate dielectric showed a field effect mobility of 0.11 cm2/Vs with no hysteresis behavior. [ABSTRACT FROM AUTHOR]

A set of direct current (DC) analytical equations is formulated for the analysis and design of a single‐layer thin‐film transistor (TFT). For a specified TFT structure, drain current is calculated as a function of drain and gate voltage (taking the source as ground) according to the Enz, Krummenacher, Vittoz (EKV) compact model. One model parameter function is required to implement this EKV‐based equation, that is, drift mobility as a function of gate voltage. Drift mobility is evaluated as a consequence of accumulation layer electrostatics assessment of the TFT structure specified. In order to implement the model, three semiconductor properties (low‐frequency (static) relative dielectric constant, free electron concentration, and maximum (no trapping) mobility), two structure properties (insulator capacitance density and TFT width‐to‐length ratio), and one physical operating parameter (temperature) must be specified. Optimal TFT mobility performance is achieved when the thickness of the semiconductor channel layer is constrained to be less than 2.22 times the channel layer Debye length such that "short‐base" TFT operation obtains. Additionally, higher mobility TFT performance is obtained by selecting a channel layer with a small electron effective mass, reducing channel layer trap density, reducing channel layer thickness, reducing the free electron concentration, and/or increasing gate capacitance density. [ABSTRACT FROM AUTHOR]

In contrast to lift-off and shadow mask processes, the back-channel wet etching (BCWE) process is suitable for industrial-scale metallization processes for the large-area and mass production of oxide thin-film transistors (TFTs). However, chemical attacks caused by the corrosive metal etchants used in the BCWE process cause unintended performance degradation of oxide semiconductors, making it difficult to implement oxide TFT circuits through industrial-scale metallization processes. Herein, we propose composition engineering of oxide semiconductors to enhance the chemical durability and electrical stability of oxide semiconductors. The chemical durability of InZnO against Al etchants can be improved by increasing the content of indium oxide, which has a higher chemical resistance than zinc oxide. As a result, A damage-free BCWE-based metallization process was successfully demonstrated for oxide TFTs using In-rich InZnO semiconductors. Furthermore, In-rich InZnO TFTs with wet-etched Al electrodes exhibited electrical performance comparable to that of lift-off Al electrodes, without chemical attack issues. [ABSTRACT FROM AUTHOR]

Metal-oxide-semiconductor (MOS)-based thin-film transistors (TFTs) are gaining significant attention in the field of flexible electronics due to their desirable electrical properties, such as high field-effect mobility (μFE), lower IOFF, and excellent stability under bias stress. TFTs have widespread applications, such as printed electronics, flexible displays, smart cards, image sensors, virtual reality (VR) and augmented reality (AR), and the Internet of Things (IoT) devices. In this study, we approach using a low-temperature solution-processed hafnium zirconium oxide (HfZrOx) gate insulator (GI) to improve the performance of lanthanum zinc oxide (LaZnO) TFTs. For the optimization of HfZrO GI, HfZrO films were annealed at 200, 250, and 300 °C. The optimized HfZrO-250 °C GI-based LaZnO TFT shows the μFE of 19.06 cm2V−1s−1, threshold voltage (VTH) of 1.98 V, hysteresis voltage (VH) of 0 V, subthreshold swing (SS) of 256 mV/dec, and ION/IOFF of ~108. The flexible LaZnO TFT with HfZrO-250 °C GI exhibits negligible ΔVTH of 0.25 V under positive-bias-temperature stress (PBTS). The flexible hysteresis-free LaZnO TFTs with HfZrO-250 °C can be widely used for flexible electronics. These enhancements were attributed to the smooth surface morphology and reduced defect density achieved with the HfZrO gate insulator. Therefore, the HfZrO/LaZnO approach holds great promise for next-generation MOS TFTs for flexible electronics. [ABSTRACT FROM AUTHOR]

This review aims to provide a technical roadmap and an overview of recent progress in the development of backplane thin film transistors (TFTs) for organic light-emitting diodes flat panel displays and next-generation flexible displays. In the introduction, we provide a general overview of the research trends for backplane TFTs. The main part describes the current technical level and prospects for amorphous metal oxide semiconducting, metal halide perovskites, and 2D transition metal dichalcogenides TFTs. The summary and prospects are provided in the conclusion section. [ABSTRACT FROM AUTHOR]