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Recent advancements in quantum photonic circuits have significantly influenced the field of quantum information processing. The pursuit of an integrated quantum photonic circuit that offers an active, stable platform for large-scale integration and high processing efficiency remains a key objective. The grating coupler, as a crucial element for an efficient transformation output interface in the integrated quantum photonic circuits, presents significant potential for practical applications. Here, we demonstrate the integration block of a highly efficient shallow-etched focusing apodized grating coupler with indium arsenide (InAs) quantum dots (QDs) in gallium arsenide (GaAs) on a SiO2 substrate for active quantum photonic circuits. The designed grating couplers possess a high efficiency over 90% in the broadband (900–930 nm) from the circuit to free space, and a nearly-perfect match with the fiber mode. Experimentally, the efficiency to free space reaches 81.8%, and the match degree with the fiber mode is high up to 92.1%. The proposed integration block offers the potential for large-scale integration of active quantum photonic circuits due to its stable solid substrate and highly performant output for quantum measurements. [ABSTRACT FROM AUTHOR]

Artificial Intelligence (AI) technology is leading the fourth industrial revolution, particularly as a key element in high-performance computing, complex data analysis, and real-time decision support systems. For the advancement and efficient implementation of these AI technologies, high-performance semiconductor chip manufacturing requires the essential technology of hybrid bonding processes. Hybrid bonding minimizes the physical distance between chips, enabling high-speed data transmission and low power consumption, thereby maximizing AI chip performance. Additionally, this process facilitates chip miniaturization, reduces manufacturing complexity, and supports economical production, thus expanding the application range of AI technologies across various industries. By enabling the integration of multi-functional chips, hybrid bonding significantly improves AI applications in fields such as automotive, healthcare, and telecommunications, contributing to the advancement of the fourth industrial revolution. In this paper, Wafer-to-Wafer (W2W) hybrid bonding system is developed to solve precision degradation issues occurring during the room-temperature hybrid bonding process. Performance evaluation and experiments conducted on the bonding system, fabricated based on optimal design, confirmed high-precision bonding performance at room temperature through precise position control to be compensate position error of wafer bonding. [ABSTRACT FROM AUTHOR]

Copyright of Micronanoelectronic Technology is the property of Micronanoelectronic Technology Editorial Office and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

3D neuromorphic hardware system is first demonstrated in neuromorphic application as on‐chip level by integrating array devices with CMOS circuits after wafer bonding (WB) and interconnection process. The memory window of synaptic device is degraded after WB and 3 Dimesional (3D) integration due to process defects and thermal stress. To address this degradation, Ag diffusion in materials of Ta2O5 and HfO2 is studied in a volatile memristor, furthermore, the interconnection and gate metal Ru are investigated to reduce defective traps of gate interface in non‐volatile memory devices. As a result, a memory window is improved over 106 in both types of devices. Improved and 3D integrated 12 × 14 array devices are identified in the synaptic characteristics according to the change of the synaptic weight from the interconnected Test Element Group (TEG) of the Complementary Metal Oxide Semiconductor (CMOS) circuits. The trained array devices present recognizable image of letters, achieving an accuracy rate of 92% when utilizing a convolutional neural network, comparing the normalized accuracy of 93% achieved by an ideal synapse device. This study proposes to modulate the memory windows up to 106 in an integrated hardware‐based neural system, considering the possibility of device degradation in both volatile and non‐volatile memory devices demonstrated by the hardware neural system. [ABSTRACT FROM AUTHOR]

The high curing temperatures required for traditional benzocyclobutene (BCB) materials have posed limitations on their applicability in high‐temperature‐sensitive fields. To address this challenge, our work focuses on the synthesis of a novel tetraphenylethylene (TPE)‐functionalized BCB monomer, TPE–BCB, achieved through the introduction of an ether bond onto the BCB's four‐membered ring via Williamson reaction. TPE–BCB demonstrates remarkable low‐temperature curing properties, characterized by a ring‐opening peak temperature of 190°C, representing a reduction of 60°C compared to conventional BCBs. Fully cured TPE–BCB resins exhibit exceptional dielectric and mechanical properties, coupled with minimal water absorption. Additionally, the incorporation of TPE with aggregation‐induced emission characteristics enhances the resins' luminescence and photolithographic capabilities. Notably, our TPE–BCB resins achieve impressive photolithography performance with a resolution ratio of up to 10 μm. In contrast to conventional BCB‐functionalized resins, TPE–BCB offers the dual advantage of low‐temperature curing and luminescence. This development marks a significant step in the advancement of low‐temperature curing BCB materials and serves as a pioneering example in the realm of multilayer wafer bonding materials. [ABSTRACT FROM AUTHOR]

High-performance germanium (Ge) lateral PIN photodetector (PD) arrays for short wave infrared (SWIR) imaging based on Ge-on-insulator (GOI) platform was proposed and demonstrated. The high-quality GOI platform with top-Ge layer thickness of 1.25 μ m and threading dislocation density of less than 105 cm−2 was prepared by using bonding and smart-cut technology. P -type and N -type regions with centrosymmetric racetrack shapes were introduced to lower the sidewall electric field and suppress the surface leakage current of the PD. Benefiting from the high-quality of the GOI platform and the unique design of lateral active regions, a low dark current of 2 nA under −1 V with outstanding rectification ratio of 2.1 × 106 were obtained at room temperature. Through constructing a vertical resonant cavity by SiO2 passivation layer and the Si/SiO2 substrate, the responsivity at 1550 nm was enhanced to 0.46 A W−1 with a high specific detectivity of 3.09 × 1010cm·Hz1/2 ·W−1 under −1 V. Ultimately, SWIR imaging was demonstrated by a Ge lateral PIN PD line array with 1 × 8 pixels under zero bias at room temperature. The results indicate that the proposed lateral Ge PD structure holds great application potential in the field of SWIR imaging. [ABSTRACT FROM AUTHOR]

Purpose: Wafer bonding is a key process for 3 D advanced packaging of integrated circuits. It requires very high accuracy for the wafer alignment. To solve the problems of large movement stroke, position calibration error and low production efficiency in optical alignment, this paper aims to propose a new wafer magnetic alignment technology (MAT) which is based on tunnel magneto resistance effect. MAT can realize micro distance alignment and reduces the design and manufacturing difficulty of wafer bonding equipment. Design/methodology/approach: The current methods and existing problems of wafer optical alignment are introduced, and the mechanism and realization process of wafer magnetic alignment are proposed. Micro magnetic column (MMC) marks are designed on the wafer by the semiconductor manufacturing process. The mathematical model of the space magnetic field of the MMC is established, and the magnetic field distribution of the MMC alignment is numerically simulated and visualized. The relationship between the alignment accuracy and the MMC diameter, MMC remanence, MMC thickness and sensor measurement height was studied. Findings: The simulation analysis shows that the overlapping double MMCs can align the wafer with accuracy within 1 µm and can control the bonding distance within the micrometer range to improve the alignment efficiency. Originality/value: Magnetic alignment technology provides a new idea for wafer bonding alignment, which is expected to improve the accuracy and efficiency of wafer bonding. [ABSTRACT FROM AUTHOR]

Abstract The high curing temperatures required for traditional benzocyclobutene (BCB) materials have posed limitations on their applicability in high‐temperature‐sensitive fields. To address this challenge, our work focuses on the synthesis of a novel tetraphenylethylene (TPE)‐functionalized BCB monomer, TPE–BCB, achieved through the introduction of an ether bond onto the BCB's four‐membered ring via Williamson reaction. TPE–BCB demonstrates remarkable low‐temperature curing properties, characterized by a ring‐opening peak temperature of 190°C, representing a reduction of 60°C compared to conventional BCBs. Fully cured TPE–BCB resins exhibit exceptional dielectric and mechanical properties, coupled with minimal water absorption. Additionally, the incorporation of TPE with aggregation‐induced emission characteristics enhances the resins’ luminescence and photolithographic capabilities. Notably, our TPE–BCB resins achieve impressive photolithography performance with a resolution ratio of up to 10 μm. In contrast to conventional BCB‐functionalized resins, TPE–BCB offers the dual advantage of low‐temperature curing and luminescence. This development marks a significant step in the advancement of low‐temperature curing BCB materials and serves as a pioneering example in the realm of multilayer wafer bonding materials.

A bonding process was developed for glass-to-glass fusion bonding using Borofloat 33 wafers, resulting in high bonding yield and high flexural strength. The Borofloat 33 wafers went through a two-step process with a pre-bond and high-temperature bond in a furnace. The pre-bond process included surface activation bonding using O2 plasma and N2 microwave (MW) radical activation, where the glass wafers were brought into contact in a vacuum environment in an EVG 501 Wafer Bonder. The optimal hold time in the EVG 501 Wafer bonder was investigated and concluded to be a 3 h hold time. The bonding parameters in the furnace were investigated for hold time, applied force, and high bonding temperature. It was concluded that the optimal parameters for glass-to-glass Borofloat 33 wafer bonding were at 550 °C with a hold time of 1 h with 550 N of applied force.

The wafer-scale fabrication of deep channel microfluidics for lab-on-a-chip applications by reactive ion etching and wafer bonding is reported. The microfluidic channels are etched in B-stage bisbenzocyclobutene (BCB) and Cytop with the latter used as a bonding agent. The channels are hermetically sealed between Borofloat glass and Si wafers by wafer bonding. Fluidic coupling is achieved in the plane of the channels via inlets and outlets that are revealed on the end facets of chips after dicing. Process techniques and details are reported for uniform coating and curing of BCB and Cytop, defining the channels with high accuracy using photolithography, dry etching the polymers using a hard mask, and sealing the channels by wafer bonding. Fluidic measurements are carried out at various flow rates and compared with modeling. The low Reynold's numbers of the channels ensure laminar flow conditions. Deep fluidic channels are less difficult to align to fluidic interfaces, they support higher flow rates and are less susceptible to clogging. In-plane fluidic coupling precludes the need to etch holes through the substrate. Our wafer-scale process was applied to 4 in. diameter wafers yielding 195 precision-aligned and hermetically sealed microfluidic chips, but is readily scalable to larger diameter wafers for volume production.

Wafer bonding of β‐Ga2O3 and N‐polar GaN single crystal substrates is demonstrated by adding ZnO as a "glue" interlayer. The wafers are fully bonded such that Newton rings are not observed. Temperature‐dependent current‐voltage (I–V) measurements are conducted on the as‐bonded Ga2O3/ZnO/N‐polar GaN test structure and after annealing at 600 °C and 1100 °C. The impact of post‐annealing temperature on the electrical and structural characteristics of the bonded samples is investigated. A consistently ohmic‐like characteristic is obtained by annealing the bonded wafers at 1100 °C in N2, which is in part due to crystallization of ZnO and diffusion of Ga into ZnO which makes it n‐type doped. The wafer bonding of β‐Ga2O3 and GaN achieved in this work is promising to combine the material merits of both GaN and Ga2O3 targeting breakthrough high‐frequency and high‐power device performances. [ABSTRACT FROM AUTHOR]

Copyright of Electronic Components & Materials is the property of Electronic Components & Materials and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

Abstract Wafer bonding of β‐Ga2O3 and N‐polar GaN single crystal substrates is demonstrated by adding ZnO as a “glue” interlayer. The wafers are fully bonded such that Newton rings are not observed. Temperature‐dependent current‐voltage (I–V) measurements are conducted on the as‐bonded Ga2O3/ZnO/N‐polar GaN test structure and after annealing at 600 °C and 1100 °C. The impact of post‐annealing temperature on the electrical and structural characteristics of the bonded samples is investigated. A consistently ohmic‐like characteristic is obtained by annealing the bonded wafers at 1100 °C in N2, which is in part due to crystallization of ZnO and diffusion of Ga into ZnO which makes it n‐type doped. The wafer bonding of β‐Ga2O3 and GaN achieved in this work is promising to combine the material merits of both GaN and Ga2O3 targeting breakthrough high‐frequency and high‐power device performances.

The quality of the silicon-buried oxide bonded interface of SOI devices created by thin Si film transfer and bonding over pre-patterned cavities, aiming at fabrication of DG and SON MOSFETs, is studied by means of chargepumping (CP) measurements. It is demonstrated that thanks to the chemical activation step, the quality of the bonded interface is remarkably good. Good agreement between values of front-interface threshold voltage determined from CP and I-V measurements is obtained.

Single-mode long-wavelength (LW) vertical-cavity surface-emitting lasers (VCSELs) present an inexpensive alternative to DFB-lasers for data communication in next-generation giga data centers, where optical links with large transmission distances are required. Narrow wavelength-division multiplexing systems demand large bit rates and single longitudinal and transverse modes. Spatial division multiplexing transmission through multicore fibers using LW VCSELs is enabling still larger-scale data center networks. This review discusses the requirements for achieving high-speed modulation, as well as the state-of-the-art. The hybrid short-cavity concept allows for the realization of f3dB frequencies of 17 GHz and 22 GHz for 1300 nm and 1550 nm range VCSELs, respectively. Wafer-fusion (WF) concepts allow the realization of long-time reliable LW VCSELs with a record single-mode output power of more than 6 mW, 13 GHz 3 dB cut-off frequency, and data rates of 37 Gbit/s for non-return-to-zero (NRZ) modulation at 1550 nm. [ABSTRACT FROM AUTHOR]

Aerosol jet printing (AJP) is an emerging additive manufacturing technology that is gaining increasing attention in the electronic field. Several studies have been carried out on the AJP of conductive, semiconductive, and dielectric polymers for electronic applications. However, wafer bonding is an application that is still uncovered by literature. Therefore, in this work, the AJP of benzocyclobutene (BCB) as a polymeric adhesive for wafer bonding is presented for the first time. A thorough characterization of the processing parameters is carried out to identify the most ideal conditions for printing at a relatively high speed. Then, square patterns are printed, proving the versatility of the AJP technology in terms of the reachable thickness of the deposited BCB patterns. Complex patterns with a resolution of ≈60 µm are also printed. The bonding properties of the BCB are characterized from a morphological and mechanical point of view. In particular, the shear strength of the BCB coatings deposited with AJP is ≈39 MPa and it is comparable with the shear strength of BCB coating deposited by spin‐coating. Consequently, AJP represents a valid alternative for the deposition of polymeric adhesive for wafer bonding. [ABSTRACT FROM AUTHOR]

Copyright of Piezoelectrics & Acoustooptics is the property of Piezoelectric & Acoustooptic and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

In this paper, Finite Element Method (FEM)-based design and simulation of circular capacitive micromachined ultrasonic transducer (CMUT) has been discussed. The FEM simulation of CMUT is accomplished by using MEMCAD tools CoventorWare® and COMSOLTM. The simulation has been performed for air-coupled CMUT devices in which the resonance frequency of the designed CMUT device is 3.9 MHz. Moreover, the simulation results for resonance frequency and pull-in voltage show good agreement with analytical calculations. Finally, a device layer transfer fabrication process flow is also proposed to develop the MEMS-based CMUT devices.

Two interfacial dislocation networks were obtained in a Si–Si material system by wafer bonding process for low twist angles around 0.2°. For one sample, one of the two initial wafers was rotated with an additional angle of 90° before the bonding. TEM analyses of samples prepared for planar and transverse views show different characteristics in terms of spatial arrangement and dislocation types. Long climbing segments slightly deviated from the [100] axis and short segments a/2<101> are arranged in the dislocation network obtained with an additional rotation and at the lowest twist angle (Ψ = 0.18°) from a <110> axis. Long screw segments a/2<110> and short partial Shockley segments are arranged in the dislocation network obtained without any additional rotation at the highest twist angle (Ψ = 0.27°) from a <110> axis. In both cases, the long and short segments form elongated hexagonal patterns, which are accurately ordered in one set paving the <100> directions or randomly ordered in two perpendicular sets paving the <110> directions, respectively. The results are discussed taking into account the arangement of the surface miscut steps in the initial wafers before the bonding. [ABSTRACT FROM AUTHOR]

[Display omitted] • A novel microfluidic heat pipe device with heterointerfaces for thermal management. • Neutral oxygen species → H 2 O two step activation builds –OH groups on the surfaces. • Low-damage heterogeneous interfaces are obtained at 150 °C under in-situ vacuum. • The bonding mechanism of the multistep bonding process was established. There has been considerable interest in low-temperature in-situ integration techniques for the fabrication of hetero-structured substrates and micro/nanosystems. This study presents a novel bonding approach that uses a water vapor-assisted surface activation strategy with neutral oxygen species (NOS). This method enables of highly efficient in-situ bonding process that utilizes the controllable and flexible environment to meet specific integration needs without exposure to the unstable ambient air. The NOS and water vapor increases hydroxyl groups, leading to smoother and more hydrophilic surfaces. The combined effects of NOS and the water vapor result in a larger bonded area ratio and significantly higher bonding energy compared to those activated by NOS alone. Meanwhile, the silicon oxide and quartz glass surfaces avoid being heavily electrically charged. This process thus achieved flawless silicon/quartz glass wafer bonding at 150 °C with a high bonding energy (∼4 J/m2) and Si/Si bonding pairs without any subsequent annealing voids. Then, the bonding pairs have been verified to have high reliability in extreme environments from −65 °C to 200 °C with no thermal-shocked cracks. The high-quality heterointerfaces could also withstand subsequent mechanical grinding and polishing for silicon-on-quartz glass (SOQ) fabrication. Moreover, a SOQ structured microfluidic heat pipe device was successfully fabricated based on the low-temperature in-situ heterogenous bonding. The robust heterointerfaces ensured non-leakage working during the heat dissipation. This facile and cost-effective bonding method is suitable for damage-free heterogeneous integration of active devices, micro/nanofluidic chips, and M/NEMS packaging. It has of great potential in fields such as biochemical analysis, quantum computing, and thermal sensing. [ABSTRACT FROM AUTHOR]

Abstract Aerosol jet printing (AJP) is an emerging additive manufacturing technology that is gaining increasing attention in the electronic field. Several studies have been carried out on the AJP of conductive, semiconductive, and dielectric polymers for electronic applications. However, wafer bonding is an application that is still uncovered by literature. Therefore, in this work, the AJP of benzocyclobutene (BCB) as a polymeric adhesive for wafer bonding is presented for the first time. A thorough characterization of the processing parameters is carried out to identify the most ideal conditions for printing at a relatively high speed. Then, square patterns are printed, proving the versatility of the AJP technology in terms of the reachable thickness of the deposited BCB patterns. Complex patterns with a resolution of ≈60 µm are also printed. The bonding properties of the BCB are characterized from a morphological and mechanical point of view. In particular, the shear strength of the BCB coatings deposited with AJP is ≈39 MPa and it is comparable with the shear strength of BCB coating deposited by spin‐coating. Consequently, AJP represents a valid alternative for the deposition of polymeric adhesive for wafer bonding.

This paper investigates a moiré-based mark for high-precision wafer bonding alignment. During alignment, the mark is combined with digital grating, which has the benefits of high precision and small size. A digital grating is superimposed on the mark to generate moiré fringes. By performing a phase calculation on the moiré fringe images corresponding to the upper and lower wafers, the relative offset of the upper and lower wafers can be accurately calculated. These moiré fringes are exceptionally stable, thereby enhancing the alignment stability. In this study, through practical experiments, we tested the rationality and practicability of the mark. [ABSTRACT FROM AUTHOR]

Laser micro‐welding is an advanced manufacturing method today applied in various domains. However, important physical limitations have prevented so far to demonstrate its applicability in silicon (Si) and other technology‐essential semiconductors. Concentrating on circumventing the optical limits on the deliverable energy density at interfaces between narrow‐gap materials with intense infrared light, the first feasibility demonstration of transmission laser welding between Si workpieces using nanosecond laser pulses is made. A shear joining strength of 32 ± 10 MPa which compares very favorably to the complex process alternatives is obtained. Supported by experiments repeated on different material combinations including gallium arsenide, it is confirmed that this remarkable performance level is achievable for similar and dissimilar semiconductors. The demonstrations rely on a small footprint fiber laser, an aspect that holds great promises for the advent of a high‐efficiency flexible process beneficial for important technology developments including lab‐on‐a‐chip and hybrid semiconductor systems. [ABSTRACT FROM AUTHOR]

Direct wafer bonding is one of the most attractive techniques for next-generation semiconductor devices, and plasma has been playing an indispensable role in the wider adoption of the wafer bonding technique by lowering its process temperature. Although numerous studies on plasma-assisted direct wafer bonding have been reported, there is still a lack of deep investigations focusing on the plasma itself. Other than the plasma surface treatment, the wafer bonding process includes multiple steps such as surface cleaning and annealing that require comprehensive studies to maximize the bonding strengths. In this work, we evaluate the various process steps of Si–SiO2 wafer bonding through case-by-case experimental studies, covering factors including the plasma conditions for surface treatment and secondary factors such as the time intervals between some process steps. The results show that plasma treatment with increasing input power has a trade-off between bonding strengths and interfacial voids, requiring the optimization of the plasma conditions. It is also noticeable that the effects of plasma treatment on wafer bonding can be improved when the plasma-treated wafers are stored in ambient atmosphere before the subsequent process step, which may suggest that wafer exposure to air during the bonding process is advantageous compared to processing entirely in vacuum. The results are expected to allow plasma-assisted direct wafer bonding technology to play a bigger role in the packaging process of semiconductor device manufacturing. [ABSTRACT FROM AUTHOR]

For radiation hardened image sensors, a Silicon-On-Insulator (SOI) -Si/ 4H-SiC hybrid pixel device was developed. The hybrid pixel device consists of one Si photodiode and three 4H-SiC nMOSFETs. At fabrication, SOI substrate was directly bonded on 4H-SiC substrate via SiO2. After bonding, the base silicon substrate and Buried Oxide (BOX) were removed by TMAH wet-etching. By using this SOI-Si/ 4H-SiC substrate, the SOI-Si photodiodes and 4H-SiC nMOSFETs were integrated in the same substrate. As a result, a response of the SOI-Si/ 4H-SiC hybrid pixel device to light illumination was successfully demonstrated. [ABSTRACT FROM AUTHOR]

In this letter, we present a photoreceiver front-end circuit that consists of an InP p-i-n photodetector (PIN PD) on an InP transimpedance amplifier (TIA) with double HBTs (DHBTs), in which the key integrated fabrication route of a transfer-printing (TP) process is introduced. Prior to integration, PDs and TIAs are individually fabricated on their respective wafers. Then, a discrete PD with only active layers is transferred onto the destination on a TIA wafer, thereafter, an on-chip coplanar waveguide connection is integrated. The PIN PD and DHBT TIA exhibit excellent performance, characterized by a responsivity of 0.51 A/W at $1.55~\mu \text{m}$ with a bandwidth of 20 GHz and a transimpedance gain of 36 dB $\Omega $ with a bandwidth of 27 GHz, respectively. Finally, the monolithically integrated circuit demonstrates a better frequency response by maximally reducing the parasitic effect, with an open clear eye diagram under a 20 Gb/s nonreturn-to-zero pattern, which evidently manifests its ability for ultrahigh-rate data operation. The present work, by employing a TP process, overcomes the issues in integrating discrete optoelectronic devices and proposes a unique approach for monolithic optoelectronic integrated circuit fabrication. [ABSTRACT FROM AUTHOR]

For next-generation system-on-chips (SoCs) in diverse applications (RF, sensor, display, etc.) which require high-performance, small form factors, and low power consumption, heterogeneous and monolithic 3D (M3D) integration employing advanced Si CMOS technology has been intriguing. To realize the M3D-based systems, it is important to take into account the relationship between the top and bottom devices in terms of thermal budget, electrical coupling, and operability when using different materials and various processes during integration and sequential fabrication. In this paper, from this perspective, we present our recent progress of III-V devices on Si bottom devices/circuits for providing informative guidelines in RF and imaging devices. Successful fabrication of the high-performance InGaAs high electron mobility transistors (HEMTs) on the bottom ICs, with a high unity current gain cutoff frequency (fT) and unity power gain cutoff frequency (fMAX) was accomplished without substrate noise. Furthermore, the insertion of an intermediate metal plate between the top and bottom devices reduced the thermal interaction. Furthermore, the InGaAs photodetectors (PDs) were monolithically integrated on Si bottom devices without thermal damage due to low process temperature. Based on the integrated devices, we successfully evaluated the device scalability using sequential fabrication and basic readout functions of integrated circuits. [ABSTRACT FROM AUTHOR]

The integration of lithium niobate (LiNbO 3 or LN) and silicon (Si) has emerged as a promising heterogeneous platform for microelectromechanical systems (MEMSs) and photonic integrated circuits (PICs). Particularly, the lithium niobate on silicon (LNOS) architecture leverages the superior piezo-optomechanical properties of LN, making it compatible with superconducting circuits and quantum systems. This opens an avenue for the development of advanced quantum sensors and processors. However, existing LN and Si bonding methods suffer from inherent limitations, such as low interfacial strength and the formation of thick, amorphous interlayers. In this work, we present an asymmetric surface activation strategy to address these challenges. By employing proton-exchange-enhanced chemical activation on the LN surface and oxygen plasma treatment on the Si side, we have achieved remarkable bonding strengths of up to 10 MPa at a moderate annealing temperature of 150 °C. Notably, the bonding mechanism in our approach differs from that in conventional diffusion-based processes. Here, the dehydration condensation of surface functional groups results in an exceptionally thin interfacial layer, less than 2 nm thick, without the presence of amorphous LN. This innovative fabrication method for LNOS demonstrates superior reliability, piezoelectric performance, thermal management capabilities, and optical transmission qualities, paving the way for cutting-edge photonic and quantum applications.

The performance of mid-infrared (MIR) on-chip gas sensors, operating via laser absorption spectroscopy, hinges critically on light-matter interaction dynamics, significantly influenced by external confinement and the effective light path length. Conventional on-chip sensors, however, face challenges in achieving the required limit of detection for highly sensitive applications, primarily due to their intrinsically short effective light path. Furthermore, these sensors are limited in their spectral range coverage within the MIR spectrum by the constraints of standard silicon-based platforms. To overcome these limitations, our research presents a novel approach to fabricate a freestanding germanium (Ge) photonic crystal waveguide (PCW) on a germanium-on-insulator (Ge-OI) platform, utilizing yttrium oxide (Y 2 O 3 ) as the buried oxide layer. This device leverages the broad transparent windows of Ge and Y 2 O 3 , broadening the spectral coverage across the MIR range. The introduction of the PCW and its slow light effect significantly elevate external confinement and light-matter interactions, enabling a notable reduction in waveguide length, which traditionally limits on-chip configurations. The freestanding structure not only expands the sensing region and enhances external confinement but also prevents the emergence of leaky modes within the PCW. As a result, our compact sensor achieves an exceptionally low LoD of 7.56 ppm for carbon dioxide (CO 2 ) sensing at the operational wavelength of 4.23 μm, with a compact waveguide length of only 800 μm.

Deposition of GaInAsP crystalline layer structures on a directly bonded InP/Si substrate for the fabrication of a laser diode device was explored using conventional metal–organic vapor-phase epitaxy (MOVPE) growth technology. In particular, one of the remarkable strategies that we have introduced is the ability to make a firm bonding of an InP epi-layer adhered to the Si substrate before the growth of the GaInAsP layer structures. In previous studies, a 1.2 μm-wavelength laser diode on InP/Si substrate was achieved. To further the research on laser growth, the epitaxial layer structures were numerically studied and analyzed. It was found that the performance of the laser was very efficient in increasing the p-cladding layer thickness. An analysis was also performed on the n-cladding layer to determine the power in the silicon substrate. When the n-cladding layer thickness was increased, the power in the silicon substrate was dramatically decreased. We realized that the n-cladding layer influences the confinement factor in the active layer. The confinement factor and threshold current density (Jth) of the n-cladding layer were also calculated numerically. In this paper, we report the numerical analysis and lasing characteristics of 1.5 µm telecommunication wavelength double-heterostructure lasers on the directly bonded InP/Si substrate and also a subsequent comparison of threshold current density between the InP/Si laser diode (LD) and the standard InP laser diode substrate. [ABSTRACT FROM AUTHOR]

We explore compatibility of Ru with Al-Ge eutectic wafer bonding. We first present experiments to check for the presence of Ru ternary alloy poisoning inhibiting Al-Ge melting as well as evaluations of Al-Ge melt wettability on Ru and diffusion outcomes following bond-simulating anneals. Results show that Ru is stable with no observed microstructural changes or dissolution in the melt, indicating no ternary poisoning for the applied thermal budget. Ru was found to act as an effective barrier offering good melt wettability in all considered configurations with Al and Ge. From inspection of the binary constituents of Al-Ge-Ru we propose that Al-Ge eutectic melting temperature will decrease marginally for Ru contamination in a 1-2% range before a drastic increase in melting temperature (>10°C/% Ru) at higher Ru compositions. We then demonstrate wafer-level packaged 200 mm devices and MEMS with strong bond outcomes of devices bearing Ru contacts. We conclude that Ru has high compatibility with Al-Ge eutectic bonding. [2022-0037] [ABSTRACT FROM AUTHOR]

Heterogeneous integration of micro-electro mechanical systems (MEMS) and complementary metal oxide semiconductor (CMOS) integrated circuits (ICs) by 3D stacking or wafer bonding is an emerging approach to advance the functionality of microdevices. Aluminum (Al) has been of interest as one of the wafer bonding materials due to its low cost and compatibility with CMOS processes. However, Al wafer bonding typically requires a high temperature of 450 ° C or more due to the stable native oxide which presents on the Al surface. In this study, a wafer bonding technique for heterogeneous integration using electroplated Al bonding frame is demonstrated. The bonding mechanism relies on the mechanical deformation of the electroplated Al bonding frame through a localized bonding pressure by the groove structures on the counter wafer, i.e., press marking. The native oxide on the surface was removed and a fresh Al surface at the bonding interface was released through such a large mechanical deformation. The wafer bonding was demonstrated at the bonding temperatures of 250–450 ° C. The influence of the bonding temperature to the quality of the bonded substrates was investigated. The bonding shear strength of 8–100 MPa was obtained, which is comparable with the other Al bonding techniques requiring high bonding temperature. [ABSTRACT FROM AUTHOR]

III–V//Si multijunction solar cells offer a pathway to increase the power conversion efficiency beyond the fundamental Auger limit of silicon single‐junctions. In this work, we demonstrate how the efficiency of a two‐terminal wafer‐bonded III–V//Si triple‐junction solar cell is increased from 34.1 % to 35.9 % under an AM1.5g spectrum, by optimising the III–V top structure. This is the highest reported efficiency to date for silicon‐based multijunction solar cell technologies. This improvement was accomplished by two main factors. First, the integration of a GaInAsP absorber in the middle cell increased the open‐circuit voltage by 51 mV. Second, a better current matching of all subcells enhanced the short‐circuit current by 0.7 mA/cm2. Two different growth directions, upright and inverted, were investigated. The highest cell efficiency of 35.9 % (Voc = 3.248 V, jsc = 13.1 mA/cm2, FF = 84.3 %) was achieved with an upright grown structure. Processing of upright structures requires additional bonding steps, which results in a reduced homogeneity of cell performance across the wafer. A detailed comparison with the currently best triple‐junction solar cell reveals future improvement opportunities and limits, considering voltage and current, respectively. [ABSTRACT FROM AUTHOR]

[Display omitted] • Single crystal SiC/SiC bonding with W or Ti layer is achieved at high temperature. • High temperature annealing results in a strongly adhesive and conductive interface. • Metal boosts SiC dissolution and atoms interdiffusion; M: Si: C phases are formed. • New crystalline phases get an epitaxial relationship with SiC substrate structure. • Dewetting for W or phase separation for Ti define the eventual interface morphology. The high temperature behavior of thin metal films (tungsten and titanium) confined between two off-axis single crystal SiC substrates is investigated. Through the application of transmission and scanning transmission electron microscopy, scanning electron microscopy, and X-ray scattering techniques, we examine the phase and morphology changes induced by high temperature annealing in thin layers consisting of these materials, as well as at their interfaces with SiC. Upon high-temperature annealing, a uniform and continuous W film formed by low-temperature deposition undergoes a transition to an array of discontinuous domains surrounded by a direct SiC/SiC interface. In contrast, a Ti film remains continuous with a strong thickness alteration. In parallel to step-bunching process of the internal SiC surfaces, both materials transform into new crystalline phases which contain Si and/or C atoms and achieve an epitaxial relationship with the SiC structures. The experimental findings are discussed in terms of dewetting phenomena and analyzed in light of potential chemical and structural reactions that may occur during interface reconstructions. [ABSTRACT FROM AUTHOR]

• Monolithic lithium niobate microfluidic chips are realized by facile fabrication. • Room temperature H 2 plasma proton exchange enhances the bonding performance. • High-density and diverse functional groups on the surface of lithium niobate. • Lithium niobate channel processing with high etching rate and smooth morphology. • The superior performance of full lithium niobate structure in SAW applications. In the quest to enhance the functionality and efficiency of lab-on-a-chip systems, integrating diverse physical phenomena such as acoustics, optics, and electronics into a single platform has emerged as a pivotal strategy. Lithium niobate (LiNbO 3 , or LN) stands out for its exceptional piezoelectric and electro-optic properties, making it an ideal candidate for such integrated systems. However, the full exploitation of LN in microfluidic applications has been hindered by the complex challenges associated with its fabrication. Addressing this gap, our research introduces a facile fabrication method for creating monolithic LN microfluidic chips. By employing a proton exchange-assisted surface-activated bonding technique, we achieve high-strength, flawless bonding at lower temperatures, overcoming the traditional barriers of LN machining. This method eliminates the chemical stability of LN by removing lithium ions and significantly enriches the surface with functional groups, leading to a bonding strength exceeding 10 MPa after annealing at 150 °C. Additionally, we have optimized an argon plasma etching process to ensure the creation of smooth LN channels at room temperature. The development of a fully integrated LN chip through this approach demonstrates superior performance, especially in surface acoustic wave (SAW) applications, compared to conventional PDMS/LN hybrids. This breakthrough not only realizes the fabrication process of LN microfluidic devices but also opens new avenues for the advancement of integrated microsystems across various scientific and technological domains. [ABSTRACT FROM AUTHOR]

The combination of ion-slicing and direct wafer bonding technology is a very promising method for transferring thin film material to cheap substrates. In this study, the evolution of internal defects and the thin film exfoliation process of He ion-implanted into LiNbO 3 crystal were studied based on ion-slicing technology. Then, based on the Ar plasma-activated bonding process, the LiNbO 3 thin film was transferred to the amorphous SiO 2 (a-SiO 2) layer. In addition, the bonding model of LiNbO 3 /a-SiO 2 /Si was established through finite element analysis, and the distribution curves of deformation and interfacial thermal stress with annealing temperature were obtained. After wet etching and proton exchange processes, the prepared LNOI substrate was successfully etched into a Y-shaped branching waveguide on the surface. The LNOI substrate prepared by this work can meet the practical application requirements of thin film LiNbO 3 devices. • The LNOI substrates was fabricated at 250 °C via the combination of ion-slicing and direct bonding technology. • Based on finite element analysis, the LiNbO 3 /a-SiO 2 /Si bonding model was established, and the interface deformation and thermal stress were analyzed. • The prepared LNOI substrate has been proven to have practical application value. [ABSTRACT FROM AUTHOR]

[Display omitted] • Bonding interface is modified to a homogenous one with an epitaxial layer. • Epitaxial layer constrains the defects, disperses and reduces the heterogenous mismatch stress. • Epitaxial layer is doped to reduce the carrier recombination leakage current in this defect-rich layer. In the realm of optoelectronic integration, silicon-based Ge bonding has attracted great attention due to its advantages in short-wave infrared response and low cost. However, owing to the inherent lattice mismatch and thermal mismatch between Ge and Si, the bonded Ge-Si heterogenous interfaces encountered problems of thermal instability and high interface states. Herein, an approach of separating the bonding interface from the heterogenous interface is proposed through inserting a Ge epitaxial layer (GeEL) between the Si substrate and Ge film. This separation modifies the bonding interface to a homogenous one, alleviating the massive mismatch stress and achieving film relaxation, enhancing bonding stability in all aspects. Moreover, during 850 °C annealing, GeEL is doped via diffusion hence realizes electric filed modulation, inhibiting the carrier recombination leakage current and trap assisted tunneling in this defect-rich layer. A Ge-Si heterogenous PIN diode prepared by this bonding method has achieved a remarkable low dark current density (1.33 mA/cm2), a low ideality factor (1.11), and a high on–off ratio (1 0 6), confirming the outstanding quality of the bonded heterojunction. This work provides great prospects for higher performance, larger scale and multi-functional Si-based heterogenous material device applications. [ABSTRACT FROM AUTHOR]

Bond strength is the most reliable criterion of the wafer bonding quality. Water stress corrosion affects the bond strength, corresponding to the measurement atmosphere and residual moisture at the bonding interface. In this study, we developed a new methodology to measure the wafer bond strength including the water stress corrosion effect under the controlled atmospheres, namely, dry atmosphere, wet atmosphere, and vacuum. The developed method experimentally demonstrates the evaluation of the water stress corrosion by the surrounding air and the interfacial water separately. Furthermore, it is also indicated that the water stress corrosion depends on the bonding methods, such that the surface activated bonding using Si intermediate layer has high durability for corrosion and the hydrophilic bonding has low durability. This study will provide a new understanding of the relation between the bonding process and the water stress corrosion effect, especially for the interfacial water. [ABSTRACT FROM AUTHOR]

High power single mode wafer-fused 1300-nm VCSELs with a gain region based on InGaAs/InAlGaAs short period superlattice are fabricated. An InP-based optical cavity and two AlGaAs/GaAs distributed Bragg reflector heterostructures were grown by molecular beam epitaõy. The current and optical confinement is provided by a lateral-structured buried tunnel junction with etching depth of $\sim 25$ nm. It is shown that optimal diameter of the buried tunnel junction for high-power single mode emission is $\sim 5$ - $6~\mu \text{m}$. The VCSEL demonstrates more than 6 mW single mode continuous-wave power and a threshold current less than 1.5 mA at 20 °C. The output optical power exceeds 1 mW at 85 °C. A -3dB modulation bandwidth up to 8 GHz and 6 GHz is obtained at 20 °C and 85 °C, respectively. The gain coefficient of $\sim 650$ cm−1 and the transparency current density of $\sim 630$ A/cm2 are estimated at zero gain-to-cavity detuning (\sim 60 °C). The ultimate low internal optical losses about 0.08 % per round-trip (distributed losses ~3.2 cm−1) at 20 °C and 0.13 % per round-trip (distributed losses ~5.5 cm−1) at 100 °C were obtained. [ABSTRACT FROM AUTHOR]

Aluminum nitride (AlN) is a ceramic material with excellent dielectric and thermal properties, and it is used in the microelectron and energy fields. Despite polishing, the roughness (rms >10 nm) of AlN wafers fabricated by sintering fails to meet the surface requirements (rms <0.5 nm) for direct wafer bonding. However, rough-surface wafer bonding of paired AlN and AlN can be achieved with the following procedure: (1) rough surfaces are activated by oxygen plasma to introduce strong capillary action, (2) reactions of AlN and bonding species (OH−) are promoted by clamping during storage and annealing and (3) low-temperature annealing (<150 °C) joins the two surfaces of AlN/AlN by synthesizing Al 2 O 3 at the bonding interface. TEM and XPS results show that a transition layer exists between bonding surfaces wherein the concentration of nitrogen decreases while that of oxygen significantly increases. [ABSTRACT FROM AUTHOR]

The combination of high-absorption indium gallium arsenide (InGaAs) with Si material (excellent avalanche characteristic) is an ideal solution for the achievement of high-gain low-noise near-infrared avalanche photodetector (APD). Traditional Si-based epitaxial InGaAs thin film suffers from high threading dislocations (TDs), leading to deterioration of noise and gain-bandwidth product (GBP) of APD. InGaAs/Si APD with GBP exceeding terahertz (THz) is reported for the first time theoretically in this work. The calculated APD is based on the semiconductor interlayer bonding in which a thin polycrystalline Si (poly-Si) bonding layer is inserted at the bonded interface to isolate the mismatched lattices of InGaAs and Si single crystals. Extreme low dark current of 10−12 A of APD at room temperature is achieved due to the absence of TDs in InGaAs layer and it is located at 10−5 A near breakdown voltage (${V}_{\text{br}}$). More importantly, a deviation of the dark and optical currents near ${V}_{\text{br}}$ due to the trapping effect of holes at InGaAs/Si bonded interface is identified. The change in gain with bias is inconsistent with the 3-dB bandwidth (BW). The 3-dB BW becomes linear versus bias with the increase in poly-Si thickness, leading to high 3-dB BW (8–10 GHz) near ${V}_{\text{br}}$. Finally, ultrahigh GBPs of 1.2 and 1.3 THz are achieved for APD with 3- and 5-nm-thick poly-Si bonding layer, respectively. This may give guidance for the fabrication of semiconductor APDs which can meet next-generation high bit-rate applications. [ABSTRACT FROM AUTHOR]

Aluminum-to-aluminum wafer bonding is a promising technique for future wafer-level packaging and heterogeneous integration. The main challenge for a successful Al-to-Al thermocompression bonding is the fast oxidation of the aluminum surface. In this article, a surface-activated Al-to-Al wafer bonding process for patterned 200-mm wafers is presented, which removes the oxide in an argon plasma and enables a high bond quality with an accurate alignment. The influence of the bonding parameters’ temperature (200 °C–300 °C), force (20–40 kN), and activation time (2.5–5 min) on the contact resistances and bonding yield is analyzed. Additionally, we modified an etch mask during wafer fabrication and thereby improved the condition of the Al pad surface, which resulted in a higher bonding quality. Based on this optimized wafer fabrication process, we achieved a high bonding yield of >85% and contact resistances in the $\text{m}\Omega $ range for bonding temperatures as low as 250 °C. This demonstrates the potential of Al-to-Al wafer bonding to create reliable interconnects for 3-D wafer-level integration. [ABSTRACT FROM AUTHOR]

The focus of this study is a detailed characterization of hybrid Cu/SiO2 wafer-to-wafer bonding interconnects after reliability testing. Hybrid bonding (or direct bond interconnect) is a technology of choice for fine pitch bonding without microbumps. The main challenge of the hybrid bonding technology is the preparation of a clean Cu/SiO2 surface with controlled Cu dishing. The Cu/Cu interface after hybrid bonding and after reliability testing was investigated by electron backscatter diffraction (EBSD) in this study. The Cu interconnects (diameter $4 ~\mu \text{m}$ and pitch $18 ~\mu \text{m}$) enclosed by SiO2 were formed by wafer-to-wafer bonding. The small diced stacks were used for subsequent reliability tests. Three types of tests were carried out: temperature shock test (TST) at −40 °C/125 °C up to 1000 cycles, isothermal storage at 150 °C, 300 °C, and 400 °C, and multiple bonding cycles. The results include a comprehensive estimation of the changes in grain diameter, grain boundaries, and texture of the interconnects. All samples showed good reliability and stayed intact after all tests. Grain refinement was observed after TST, storage at 150 °C, and multiple bonding cycles compared to the state after bonding. Grain growth was found for the storage at 300 °C/400 °C (up to 6 h). No significant changes in texture was found after the reliability tests. The $\langle 111\rangle $ direction with its characteristic $\langle 115\rangle $ twin orientation is the dominating orientations perpendicular to the bonding interface. The migration of 60° twin boundaries has been observed after reliability testing. The results indicate a rotation toward nearby high-angle grain boundaries (HAGBs, 60°–45°). [ABSTRACT FROM AUTHOR]

A thin Si layer transfer process for monolithic 3D (M3D) integration is proposed using hydrogen ion (H+) implantation. The upper Si layer was transferred to CMOS circuits fabricated on the lower substrate by H+ implantation, oxide-to-oxide bonding, and a cleavage process at low temperature (< 500 °C). The M3D system comprising the photosensor connected to the CMOS device was demonstrated, where the thickness and roughness of the transferred Si layer were determined by H+ implantation and subsequent processes. The hetero-junctional photosensor was fabricated on the transferred Si layer, which generated the photocurrent ($\text{I}_{\text {ph}}$) by light exposure. The photosensor and ring oscillator circuits of the vertical structure implemented by the M3D process generated the $\text{I}_{\text {ph}}$ according to the light exposure intensity and showed different frequency behaviors accordingly. Compared with the continuous device scaling approach, M3D may be an alternative scheme for low-power, high-performance, and multi-functional devices. [ABSTRACT FROM AUTHOR]