A Low-Power Low-Complexity Multi-Standard Digital Receiver for Joint Clock Recovery and Carrier Frequency Offset Calibration.

This paper presents a novel multi-standard digital low-IF receiver, which provides low-power low-complexity, flexible and robust performance for short distance communication applications. Over the various incoming data rates and carrier frequencies, the corresponding symbol timing is recovered by the \mmb\Sigma\Delta modulated frequency divider from fractional-N synthesizer, and the carrier frequency offset is calibrated by direct digital synthesizer generated intermediate frequency. The proposed digital receiver is fully integrated with 130 nm CMOS technology, occupying 0.83 mm^2 area with 4.5 mW. Through the verification in an FPGA, the measurement results show a great potential in flexible and cost oriented applications. [ABSTRACT FROM AUTHOR]