Back to Search
Start Over
A 5.4-Gb/s Clock and Data Recovery Circuit Using Seamless Loop Transition Scheme With Minimal Phase Noise Degradation.
- Source :
-
IEEE Transactions on Circuits & Systems. Part I: Regular Papers . Nov2012, Vol. 59 Issue 11, p2518-2528. 11p. - Publication Year :
- 2012
-
Abstract
- This paper presents a 5.4-Gb/s clock and data recovery circuit using a seamless loop transition scheme which has minimal phase noise degradation. The proposed scheme enables the CDR circuit to change the operation mode without output phase noise degradation or stability problems. A modified half-rate linear phase detector reduces the phase error between the data and clock. A tested chip is manufactured using 0.13-μm CMOS technology. The rms jitter of the proposed CDR circuit is 5.98 ps-rms, which is 2.61 ps lower than the CDR circuit with the conventional scheme. The measured power dissipation is 138 mW with output drivers and an embedded 2:1 MUX at 5.4-Gb/s data rate. [ABSTRACT FROM PUBLISHER]
Details
- Language :
- English
- ISSN :
- 15498328
- Volume :
- 59
- Issue :
- 11
- Database :
- Academic Search Index
- Journal :
- IEEE Transactions on Circuits & Systems. Part I: Regular Papers
- Publication Type :
- Periodical
- Accession number :
- 101316785
- Full Text :
- https://doi.org/10.1109/TCSI.2012.2190678