Back to Search
Start Over
A Novel Low Gate-Count Pipeline Topology With Multiplexer-Flip-Flops for Serial Link.
- Source :
-
IEEE Transactions on Circuits & Systems. Part I: Regular Papers . Nov2012, Vol. 59 Issue 11, p2600-2610. 11p. - Publication Year :
- 2012
-
Abstract
- This paper proposes multiplexer-flip-flops (MUX-FFs) to be a high-throughput and low-cost solution for serial link transmitters. We also propose multiplexer-latches (MUX-Latches) that possess the logic function of combinational circuits and storing capacity of sequential circuits. Adopting the pipeline with MUX-FFs, which are composed of cascaded latches and MUX-Latches, many latch gates for sequencing can be removed. Analysis and simulation results show that an 8-to-1 serializer in the pipeline topology with MUX-FFs reduces 52% gate-count compared to that in the traditional pipeline topology. To verify the functions of the proposed design, two chips are implemented with the proposed 4-to-1 MUX-FF and 8-to-1 serializer with MUX-FFs in 90 nm CMOS technology. The measured results show that the MUX-FF and the proposed serializer with MUX-FFs are almost bit-error-free (with BER <; 10-12 ), operating at up to 6 Gbits/s and 12 Gbit/s, respectively. [ABSTRACT FROM PUBLISHER]
- Subjects :
- *POLYHEDRA
*TOPOLOGY
*GEOMETRY
*MATHEMATICS
*CMOS amplifiers
Subjects
Details
- Language :
- English
- ISSN :
- 15498328
- Volume :
- 59
- Issue :
- 11
- Database :
- Academic Search Index
- Journal :
- IEEE Transactions on Circuits & Systems. Part I: Regular Papers
- Publication Type :
- Periodical
- Accession number :
- 101316794
- Full Text :
- https://doi.org/10.1109/TCSI.2012.2206494