Back to Search
Start Over
An 8–11 Gb/s Reference-Less Bang-Bang CDR Enabled by “Phase Reset”.
- Source :
-
IEEE Transactions on Circuits & Systems. Part I: Regular Papers . Jul2014, Vol. 61 Issue 7, p2129-2138. 10p. - Publication Year :
- 2014
-
Abstract
- This paper embeds a “phase-reset” scheme into a bang-bang clock and data recovery (CDR) to periodically realign the clock phase to the data rising edge using a gated-VCO. This reduces both the CDR lock time and bit errors during pull-in, while increasing the CDR capture range. The CDR is fabricated in 65-nm CMOS, operates at 8-11 Gb/s, and demonstrates a 9 × increase in capture range. The CDR consumes 84 mW during lock, and 48 mW in steady state. [ABSTRACT FROM AUTHOR]
Details
- Language :
- English
- ISSN :
- 15498328
- Volume :
- 61
- Issue :
- 7
- Database :
- Academic Search Index
- Journal :
- IEEE Transactions on Circuits & Systems. Part I: Regular Papers
- Publication Type :
- Periodical
- Accession number :
- 101316829
- Full Text :
- https://doi.org/10.1109/TCSI.2014.2304668