Simulator-independent compact modeling of vertical npn transistors for ESD and RF circuit simulation

We present an easy-to-use, simulator-independent compact model of a vertical npn transistor suitable for ESD circuit simulation. In addition to including high-current and breakdown effects, we also model accurately the small-signal off-state impedance of the device using <f>s</f>-parameter measurements, for inclusion in RF circuit simulations. Experimental results are provided for silicon and SiGe npn transistors. [Copyright &y& Elsevier]