Simplistic Simulation-Based Device-VT-Targeting Technique to Determine Technology High-Density LELE-Gate-Patterned FinFET SRAM in Sub-10 nm Era.

For the first time, we present complete device threshold voltage (VT)-targeting methodology for FinFET SRAM in 10-nm technology, considering capacitance due to metal pattering and device variability to set target read current for different variants of SRAM architecture to determine technology high-density (HD) SRAM cell. The VT-targeting methodology brings into play the worst case read and write margins available for SRAM cell to determine nominal device VT by tuning the work function of metal gate. Analysis shows that for minimum leakage current, 112 SRAM cell is optimum, whereas for the same area of 0.0546~\mu \mathrm{m}^{\mathrm {2}} with 50% higher leakage, 122 SRAM outperform by 5% and 20% improved read and write margins, respectively. The 122 SRAM as HD cell reduces the cost of the technology by sharing P-channel field effect transistor (PFET) and N-channel field effect transistor (NFET) VT mask with the high threshold voltage logic devices, whereas the 112 SRAM device shares only NFET VT mask. The 111 SRAM can achieve target performance at lesser area of 0.048~\mu \mathrmm^\mathrm 2 by compromising read stability, which will result in lower yield. At 64-nm pitch, litho-etch litho-etch (LELE) double-patterned gate impacts device performance and alleviates variability; hence the read margin of SRAM cell should consider an additional 1\sigma \mathrm {\mathbf {rsnm}} margin to retain the same yield in 10-nm-technology era. [ABSTRACT FROM AUTHOR]