Q-Band Spatially Combined Power Amplifier Arrays in 45-nm CMOS SOI.

This paper reports 45-GHz power amplifier (PA) arrays implemented in 45-nm CMOS silicon-on-insulator, coupled to antenna arrays to enable free-space power combining. A single CMOS chip (2.5\,\times\,4.5 \mm^2) containing eight-unit PAs was developed and its output was fed to a 2\,\times\,2 array of differentially fed patch antennas on a printed circuit board. This array provided an equivalent isotropic radiated power (EIRP) of 40 dBm at 45 GHz with 28 dBm of total RF power generated by the chip. A larger array, composed of four CMOS chips and feeding a 2\,\times\,8 array of antennas, was shown to deliver an EIRP of 50 dBm at 45 GHz, while generating a total RF power of 33 dBm together with an antenna array gain of 17 dB. The dc power consumptions for the \2\,\times\,\2 and the 2\,\times\,8 arrays were 4.9 and 18 W, respectively, with estimated peak power-added efficiencies of 13.5% and 10.7%. [ABSTRACT FROM PUBLISHER]