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Automatic Placement to Improve Capacitance Matching Using a Generalized Common-Centroid Layout and Spatial Correlation Optimization.
- Source :
-
IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems . Oct2015, Vol. 34 Issue 10, p1691-1695. 5p. - Publication Year :
- 2015
-
Abstract
- In analog designs, the most widely adopted layout practice to improve matching is the symmetrical common-centroid placement. However, this arrangement cannot be obtained in general. In this paper, it is shown that there are asymmetrical placements with a common centroid which are also immune to process gradients and suitable for designs where a symmetrical layout is not possible. In addition, this paper proposes an automated method, based on a standard simulated annealing framework, to arrange fully-integrated capacitors in a layout to improve their matching. [ABSTRACT FROM PUBLISHER]
- Subjects :
- *CENTROID
*CAPACITORS
*INTEGRATED circuits
*SYMMETRIC functions
*SIMULATED annealing
Subjects
Details
- Language :
- English
- ISSN :
- 02780070
- Volume :
- 34
- Issue :
- 10
- Database :
- Academic Search Index
- Journal :
- IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems
- Publication Type :
- Academic Journal
- Accession number :
- 109904086
- Full Text :
- https://doi.org/10.1109/TCAD.2015.2419624