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Jointly Designed Nonbinary LDPC Convolutional Codes and Memory-Based Decoder Architecture.
- Source :
-
IEEE Transactions on Circuits & Systems. Part I: Regular Papers . Oct2015, Vol. 62 Issue 10, p2523-2532. 10p. - Publication Year :
- 2015
-
Abstract
- In this paper, a design approach for architecture- aware nonbinary low-density parity-check convolutional codes (NB-LDPC-CCs) is presented to jointly optimizes the code performance and decoder complexity for achieving high energy-efficiency decoder. The proposed NB-LDPC-CCs not only feature simple structure and low degree, but also compete with other published NB-LDPC-CCs on error-correction capability. With these codes, we present a memory-based layered decoder architecture, where the computation units and the scheduling of the computations are optimized to increase energy efficiency. To demonstrate the feasibility of proposed techniques, a time-varying (50,2,4) NB-LDPC-CC over GF(256) is constructed, and associated decoder is implemented in 90 nm CMOS. The code can reach BER=10^-5 at SNR=0.9\ dB, and support multi code rates with puncturing. Comparing with the state-of-the-art designs, the proposed decoder can save 74% power under the same number of iterations, making it suitable for emerging Internet of Things (IoT) applications. [ABSTRACT FROM AUTHOR]
Details
- Language :
- English
- ISSN :
- 15498328
- Volume :
- 62
- Issue :
- 10
- Database :
- Academic Search Index
- Journal :
- IEEE Transactions on Circuits & Systems. Part I: Regular Papers
- Publication Type :
- Periodical
- Accession number :
- 109994076
- Full Text :
- https://doi.org/10.1109/TCSI.2015.2471575