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Efficient multi-Gb/s multi-mode LDPC decoder architecture for IEEE 802.11ad applications.
- Source :
-
Integration: The VLSI Journal . Sep2015, Vol. 51, p21-36. 16p. - Publication Year :
- 2015
-
Abstract
- This paper presents a novel multi-Gb/s multi-mode LDPC decoder architecture and efficient design techniques for gigabit wireless communications. An efficient dynamic and fixed column-shifting scheme is presented for multi-mode architectures. A novel low-complexity local switch is proposed to implement the dynamic and fixed column-shifting scheme. Furthermore, an efficient quantization method and the usage of a one׳s-complement scheme instead of a two׳s-complement scheme are explored. The proposed decoder achieves very high throughput with minimal area overhead. Post layout results using TSMC 65-nm CMOS technology shows much better throughput, as well as better area- and energy-efficiency, compared to other multi-mode LDPC decoders. [ABSTRACT FROM AUTHOR]
Details
- Language :
- English
- ISSN :
- 01679260
- Volume :
- 51
- Database :
- Academic Search Index
- Journal :
- Integration: The VLSI Journal
- Publication Type :
- Academic Journal
- Accession number :
- 110101066
- Full Text :
- https://doi.org/10.1016/j.vlsi.2015.05.001