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Background Calibration Techniques for Multistage Pipelined ADCs With Digital Redundancy.
- Source :
-
IEEE Transactions on Circuits & Systems Part II: Analog & Digital Signal Processing . Sep2003, Vol. 50 Issue 9, p531-538. 8p. 2 Black and White Photographs, 11 Diagrams, 4 Graphs. - Publication Year :
- 2003
-
Abstract
- Presents the details of a fast and accurate correlation-based background digital calibration scheme in the context of a 1.5-bit-per-stage pipelined or cyclic analog-to-digital converters architecture. Capacitor mismatch; Digital redundancy; Pseudorandom noise sequence.
- Subjects :
- *ANALOG-to-digital converters
*CALIBRATION
*CAPACITORS
Subjects
Details
- Language :
- English
- ISSN :
- 10577130
- Volume :
- 50
- Issue :
- 9
- Database :
- Academic Search Index
- Journal :
- IEEE Transactions on Circuits & Systems Part II: Analog & Digital Signal Processing
- Publication Type :
- Academic Journal
- Accession number :
- 11010389
- Full Text :
- https://doi.org/10.1109/TCSII.2003.816921