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Benchmarking of MoS2 FETs With Multigate Si-FET Options for 5 nm and Beyond.

Authors :
Agarwal, Tarun
Yakimets, Dmitry
Raghavan, Praveen
Radu, Iuliana
Thean, Aaron
Heyns, Marc
Dehaene, Wim
Source :
IEEE Transactions on Electron Devices. Dec2015, Vol. 62 Issue 12, p4051-4056. 6p.
Publication Year :
2015

Abstract

In this paper, we benchmark the performance of monolayer and bilayer MoS2 FETs (MFETs) against various multigate (MuG) Si-FET options, such as FinFETs and lateral and vertical nanowire FETs, for a 5-nm node and beyond. We compare the performance metrics of all the device options at the ring-oscillator (RO) level, accounting for not only intrinsic and extrinsic parasitic elements but also interconnects. Using the atomistic two-band ballistic quantum transport simulations, we evaluate ON-current and intrinsic capacitances for MoS2-based devices. Furthermore, we calibrate two-band model currents with more sophisticated full-band diffusive simulations to obtain realistic performance metrics at the circuit level. We show that both the intrinsic and parasitic capacitances of a single-gate MFET are lesser than those of a double-gate (DG) MFET, resulting in 13% lesser energy consumption. A DG bilayer (DGBL) MFET shows the best performance among different MFETs. In comparison toMuG FETs, the DGBL MFET offers not only lower energy consumption but also 35%–45% lower speed. In the end, to meet the target performance, we evaluate the impact of the device current, contact resistance, and back-end-of-the-line load on the speed of RO with the DGBL MFET. [ABSTRACT FROM PUBLISHER]

Details

Language :
English
ISSN :
00189383
Volume :
62
Issue :
12
Database :
Academic Search Index
Journal :
IEEE Transactions on Electron Devices
Publication Type :
Academic Journal
Accession number :
111177444
Full Text :
https://doi.org/10.1109/TED.2015.2491021