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Optimized Common-Mode Voltage Reduction PWM for Three-Phase Voltage-Source Inverters.
- Source :
-
IEEE Transactions on Power Electronics . Apr2016, Vol. 31 Issue 4, p2959-2969. 11p. - Publication Year :
- 2016
-
Abstract
- In this paper, two new optimized common-mode voltage reduction PWM (CMVRPWM) strategies based on solving the established constrained nonlinear programming models in the time domain are proposed and analyzed. The proposed current ripple losses-optimized CMVRPWM (CRLO-CMVRPWM) minimizes the mean-square values of the three-phase current ripples by calculating the optimized special solutions of the voltage–second balance equations under the designed switching sequences. CRLO-CMVRPWM can achieve better output waveform quality than the existing methods. The proposed switching losses-optimized CMVRPWM (SLO-CMVRPWM) online optimizes the bus-clamping styles according to the phase currents to minimize the switching losses under different load power factors. Compared to the near-state PWM with fixed bus-clamping styles, SLO-CMVRPWM can reduce more switching losses in broader range of the modulation index. Simulation and experimental results verify the superiority of the proposed strategies to the conventional ones. [ABSTRACT FROM PUBLISHER]
Details
- Language :
- English
- ISSN :
- 08858993
- Volume :
- 31
- Issue :
- 4
- Database :
- Academic Search Index
- Journal :
- IEEE Transactions on Power Electronics
- Publication Type :
- Academic Journal
- Accession number :
- 111308912
- Full Text :
- https://doi.org/10.1109/TPEL.2015.2451673