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Errata to “Surface-Potential-Based Drain Current Analytical Model for Triple-Gate Junctionless Nanowire Transistors”.

Authors :
Trevisoli, Renan
Doria, Rodrigo Trevisoli
de Souza, Michelly
Das, Samaresh
Ferain, Isabelle
Pavanello, Marcelo Antonio
Source :
IEEE Transactions on Electron Devices. Jan2016, Vol. 63 Issue 1, p527-527. 1p.
Publication Year :
2016

Abstract

In the paper <xref ref-type="bibr" rid="ref1">[1]</xref>, the authors would like to make the following corrections. <list list-type="ordered"><list-item><label>1)</label><p>Equation (11) needs to be read as <disp-formula> \begin{equation*} V_{G2} =V_{FB} -V_{FB} \frac {\ln [1\!+\exp (A_{1} (1\!-\!(V_{G} \!-\!Vy)/V_{FB} ))] }{\ln [1+\exp (A_{1} )] }. \end{equation*} </disp-formula> [ABSTRACT FROM AUTHOR]

Details

Language :
English
ISSN :
00189383
Volume :
63
Issue :
1
Database :
Academic Search Index
Journal :
IEEE Transactions on Electron Devices
Publication Type :
Academic Journal
Accession number :
111983700
Full Text :
https://doi.org/10.1109/TED.2015.2496962