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III–V Nanowire Transistors for Low-Power Logic Applications: A Review and Outlook.
- Source :
-
IEEE Transactions on Electron Devices . Jan2016, Vol. 63 Issue 1, p223-234. 12p. - Publication Year :
- 2016
-
Abstract
- III–V semiconductors, especially InAs, have much higher electron mobilities than Si and have been considered as promising candidates for n-channel materials for post-Si low-power CMOS logic applications. Combined with the inherent 3-D structure that enables the gate-all-around (GAA) geometry for superb gate electrostatic control, III–V nanowire (NW) MOSFETs are well positioned to extend the scaling beyond Si. This paper attempts to provide a review of the growth and fabrication approaches (both bottom–up and top–down), and the state-of-the-art device performance of III-V NW GAA MOSFETs, as well as an outlook of their scaling potential. [ABSTRACT FROM AUTHOR]
Details
- Language :
- English
- ISSN :
- 00189383
- Volume :
- 63
- Issue :
- 1
- Database :
- Academic Search Index
- Journal :
- IEEE Transactions on Electron Devices
- Publication Type :
- Academic Journal
- Accession number :
- 111983723
- Full Text :
- https://doi.org/10.1109/TED.2015.2498923