Performance Improvement of Poly-Si Tunnel FETs by Trap Density Reduction.

In this brief, the tunnel FETs (TFETs) with a polycrystalline-Si (poly-Si) channel have been demonstrated, and the performance of the poly-Si TFET shows a significant improvement by the reduction of interface trap states ( N\mathrm {{it}} ) near the conduction band edge. The ON-state current ( I\mathrm{\scriptscriptstyle ON} ) conduction mechanism, band-to-band tunneling, of poly-Si TFETs is strongly affected by the band bending of poly-Si channel. The N2 plasma surface treatment before the gate dielectric deposition can produce a plasma-induced interfacial layer to reduce N\mathrm {it} obviously, which greatly enhances the surface potential modulation by the gate and improves the I\mathrm{\scriptscriptstyle ON} value of poly-Si TFETs \sim 3.7\times . The OFF-state current ( I_{\mathrm { {min}}} ) attributed to the trap-assisted tunneling (TAT) can also be reduced by a factor of \sim 40 %, because of the passivation of grain boundary trap ( N\mathrm {trap} ) of the poly-Si channel film. Consequently, the ON/OFF current ratio is enhanced from 9.42\times 10^{5} to 6.13\times 10^6 . In addition, the subthreshold swing, $I_{{\mathrm{\scriptscriptstyle ON}}}$ , and I_{\mathrm { {min}}} of poly-Si TFET exhibit superior short-channel effect immunity, which shows good feasibility for implementing high packing density of poly-Si thin-film transistors, such as 3-D nonvolatile memory and pixel driving device. [ABSTRACT FROM AUTHOR]