Cite
Layout-based Single Event Mitigation Techniques for Dynamic Logic Circuits.
MLA
Wang, Haibin, et al. “Layout-Based Single Event Mitigation Techniques for Dynamic Logic Circuits.” Journal of Electronic Testing, vol. 32, no. 1, Feb. 2016, pp. 97–103. EBSCOhost, https://doi.org/10.1007/s10836-015-5559-8.
APA
Wang, H., Li, M., Dai, X., Shi, S., Chen, L., & Guo, G. (2016). Layout-based Single Event Mitigation Techniques for Dynamic Logic Circuits. Journal of Electronic Testing, 32(1), 97–103. https://doi.org/10.1007/s10836-015-5559-8
Chicago
Wang, Haibin, Mulong Li, Xixi Dai, Shuting Shi, Li Chen, and Gang Guo. 2016. “Layout-Based Single Event Mitigation Techniques for Dynamic Logic Circuits.” Journal of Electronic Testing 32 (1): 97–103. doi:10.1007/s10836-015-5559-8.