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Architectural strategies in standard-cell design for the 7 nm and beyond technology node.
- Source :
-
Journal of Micro/Nanolithography, MEMS & MOEMS . Jan-Mar2016, Vol. 15 Issue 1, p1-11. 11p. - Publication Year :
- 2016
-
Abstract
- Standard-cell design and characterization are presented for 7-nm CMOS platform technology targeting low-power and high-performance applications with the tightest contacted poly pitch of 42 nm and a metallization pitch of 32 nm in the FinFET technology. Two standard-cell architectures for 7 nm, a 9-track library and a 7.5-track library have been designed, introducing an extra middle-of-line layer to enable an efficient layout of the 7.5-track cells. The 7.5-track cells are on average smaller than the 9-track cells. With the strict design constraints imposed by self-aligned quadruple patterning and self-aligned double patterning, careful design and technology co-optimization is performed. [ABSTRACT FROM AUTHOR]
Details
- Language :
- English
- ISSN :
- 19325150
- Volume :
- 15
- Issue :
- 1
- Database :
- Academic Search Index
- Journal :
- Journal of Micro/Nanolithography, MEMS & MOEMS
- Publication Type :
- Academic Journal
- Accession number :
- 113697959
- Full Text :
- https://doi.org/10.1117/1.JMM.15.1.013507