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Dual-Gate JFET Modeling II: Source Pinchoff Voltage and Complete I\textrm {ds} Modeling Formalism.
- Source :
-
IEEE Transactions on Electron Devices . Apr2016, Vol. 63 Issue 4, p1416-1422. 7p. - Publication Year :
- 2016
-
Abstract
- This paper studies the phase diagram of source pinchoff of dual-gate JFETs and presents a source pinchoff modeling formalism that is smooth across the phase boundaries. Based on this, an I\textrm {ds} model is derived, which is numerically robust for any value of top- and bottom-gate voltages. The method is applied to both the exact model for I\textrm {ds} and an approximated form based on mid-point-potential linearization, and is verified by comparison with numerical simulation. Modeling of short-channel effects is included. [ABSTRACT FROM AUTHOR]
Details
- Language :
- English
- ISSN :
- 00189383
- Volume :
- 63
- Issue :
- 4
- Database :
- Academic Search Index
- Journal :
- IEEE Transactions on Electron Devices
- Publication Type :
- Academic Journal
- Accession number :
- 114035663
- Full Text :
- https://doi.org/10.1109/TED.2016.2521759