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A 10-Transistor 65 nm SRAM Cell Tolerant to Single-Event Upsets.
- Source :
-
Journal of Electronic Testing . Apr2016, Vol. 32 Issue 2, p137-145. 9p. - Publication Year :
- 2016
-
Abstract
- A novel SRAM cell tolerant to single-event upsets (SEUs) is presented in this paper. By adding four more transistors inside, the proposed circuit can obtain higher critical charge at each internal node compared to the conventional 6-transistor (6T) cell. Arrays of 2k-bit capacitance of these two designs were implemented in a 65 nm CMOS bulk technology for comparison purpose. Radiation experiments showed that, at the nominal 1.0 V supply voltage, the proposed cell achieves 47.1 % and 49.3 % reduction in alpha and proton soft error rates (SER) with an area overhead of 37 %. [ABSTRACT FROM AUTHOR]
Details
- Language :
- English
- ISSN :
- 09238174
- Volume :
- 32
- Issue :
- 2
- Database :
- Academic Search Index
- Journal :
- Journal of Electronic Testing
- Publication Type :
- Academic Journal
- Accession number :
- 114120953
- Full Text :
- https://doi.org/10.1007/s10836-016-5573-5