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A Compact 3-D VLSI Classifier Using Bagging Threshold Network Ensembles.
- Source :
-
IEEE Transactions on Neural Networks . Sep2003, Vol. 14 Issue 5, p1097-1109. 13p. - Publication Year :
- 2003
-
Abstract
- A bagging ensemble consists of a set of classifiers trained independently and combined by a majority vote. Such a combination improves generalization performance but can require large amounts of memory and computation, a serious drawback for addressing portable real-time pattern recognition applications. We report here a compact three-dimensional (3-D) multiprecision very large-scale integration (VLSI) implementation of a bagging ensemble. In our circuit, individual classifiers are decision trees implemented as threshold networks-one layer of threshold Logic units (TLU5) followed by combinatorial logic functions. The hardware was fabricated using 0.7-μm CMOS technology and packaged using MCM-V micro-packaging technology. The 3-D chip implements up to 192 TLUs operating at a speed of up to 48GCPPS and implemented in a volume of (w × L × h) = (2 × 2 × 0.7) cm3. The 3-D circuit features a high level of programmability and flexibility offering the possibility to make an efficient use of the hardware resources in order to reduce the power consumption. Successful operation of the 3-D chip for various precisions and ensemble sizes is demonstrated through an electronic nose application. [ABSTRACT FROM AUTHOR]
- Subjects :
- *ARTIFICIAL neural networks
*DECISION trees
*TECHNOLOGY
Subjects
Details
- Language :
- English
- ISSN :
- 10459227
- Volume :
- 14
- Issue :
- 5
- Database :
- Academic Search Index
- Journal :
- IEEE Transactions on Neural Networks
- Publication Type :
- Academic Journal
- Accession number :
- 11610917
- Full Text :
- https://doi.org/10.1109/TNN.2003.816362