A CUDA-based parallel implementation of a test vectors encoding algorithm in compression-based scan designs.

Compression-based scan designs, although widely adopted, are costly in power dissipation. Therefore, several techniques have been proposed to reduce power dissipation in compression-based reconfigurable scan architectures. Incorporating power reduction as an objective in selecting the configuration of reconfigurable scan architecture increases the computational runtime as all the encoding configurations must be evaluated rather than the first valid configuration. In this paper, we present a parallel implementation, using computed unified device architecture, to a test vectors encoding algorithm in compression-based scan designs. The proposed implementation exploits the independence of scan chains and test vectors to improve the performance. Experimental results indicate that the parallel algorithm can be seven times faster than the serial algorithm. [ABSTRACT FROM PUBLISHER]