Cite
Device-Circuit Cosimulation for Energy Efficiency in Sub-10-nm Gate Length Logic and Memory.
MLA
Cho, Woo-Suhl, and Kaushik Roy. “Device-Circuit Cosimulation for Energy Efficiency in Sub-10-Nm Gate Length Logic and Memory.” IEEE Transactions on Electron Devices, vol. 63, no. 7, July 2016, pp. 2879–86. EBSCOhost, https://doi.org/10.1109/TED.2016.2567385.
APA
Cho, W.-S., & Roy, K. (2016). Device-Circuit Cosimulation for Energy Efficiency in Sub-10-nm Gate Length Logic and Memory. IEEE Transactions on Electron Devices, 63(7), 2879–2886. https://doi.org/10.1109/TED.2016.2567385
Chicago
Cho, Woo-Suhl, and Kaushik Roy. 2016. “Device-Circuit Cosimulation for Energy Efficiency in Sub-10-Nm Gate Length Logic and Memory.” IEEE Transactions on Electron Devices 63 (7): 2879–86. doi:10.1109/TED.2016.2567385.