Ultralow Capacitance Transient Voltage Suppressor Design.

A novel transient voltage suppressor (TVS) that features ultralow capacitance is proposed. This structure is able to reduce the input capacitance by 21.1%, and is designed to protect against electrostatic discharge (ESD) issues for high-speed ports. The device is also able to withstand IEC 61000-4-2 contact testing at ±14 kV and transmission line pulse (TLP) testing at 20 A. The device is fabricated using a typical planar Bipolar-CMOS-DMOS (BCD) process. By slotting the doping well to decrease the concentration of diodes, a TVS with an ultralow Cj is obtained without the need to add to the process procedures or without damaging the ESD capability. [ABSTRACT FROM PUBLISHER]