Effect of low temperature anneals and nonthermal treatments on the properties of gap fill oxides used in SiGe and III-V devices.

Silicon dioxide is used to electrically isolate CMOS devices such as fin field effect transistors by filling gaps between the devices (also known as shallow trench isolation). The gap fill oxide typically requires a high temperature anneal in excess of 1000 °C to achieve adequate electrical properties and oxide densification to make the oxide compatible with subsequent fabrication steps such as fin reveal etch. However, the transition from Si-based devices to high mobility channel materials such as SiGe and III-V semiconductors imposes more severe thermal limitations on the processes used for device fabrication, including gap fill oxide annealing. This study provides a framework to quantify and model the effect of anneal temperature and time on the densification of a flowable silicon dioxide as measured by wet etch rate. The experimental wet etch rates allowed the determination of the activation energy and anneal time dependence for oxide densification. Dopant and self-diffusion can degrade the channel material above a critical temperature. We present a model of self-diffusion of Ge and Si in SiGe materials. Together these data allowed us to map the thermal process space for acceptable oxide wet etch rate and self-diffusion. The methodology is also applicable to III-V devices, which require even lower thermal budget. The results highlight the need for nonthermal oxide densification methods such as ultraviolet (UV) and plasma treatments. We demonstrate that several plasma treatments, in place of high temperature annealing, improved the properties of flowable oxide. In addition, UV curing prior to thermal annealing enables acceptable densification with dramatically reduced anneal temperature. [ABSTRACT FROM AUTHOR]