System Verilog: Ready, set, code.

This article focuses on SystemVerilog hardware description and verification language introduced as of December 15, 2003. The language has far broader capabilities, more complex syntax and a whole new learning curve. It is designed to be fully backward-compatible with Verilog language, while incorporating a host of new features by means of technology donations from such companies as Co-Design Automation Inc., Synopsys Inc., Verplex Systems and Intel Corp. Management will enjoy the productivity benefits of a common language for design and verification. The complex transition from system model to implementation will be greatly eased.