Controlling L-BTBT and Volume Depletion in Nanowire JLFETs Using Core–Shell Architecture.

In this paper, we propose the use of a p+ core in the core–shell nanowire (CS NW) architecture to significantly reduce the gate induced drain leakage and therefore, increase the ON-state to OFF-state current ratio ( $I_{{\mathrm{\scriptscriptstyle ON}}}/I_{{\mathrm{\scriptscriptstyle OFF}}}$ ) in n-NW junctionless FETs (NWJLFETs). We show that the lateral band-to-band tunneling induced parasitic bipolar junction transistor action is diminished in the CSJLFET due to an enhanced tunneling width and a higher source to channel barrier height. Further, we also demonstrate that the p+ core helps to realize efficient volume depletion in NWJLFETs with large NW width. Using calibrated 3-D simulations, we show that the CSJLFET exhibits a significantly high ON-state to OFF-state current ratio ( $I_{{\mathrm{\scriptscriptstyle ON}}}/I_{{\mathrm{\scriptscriptstyle OFF}}}$ ) of \sim 10^{7} even for a channel length of 7 nm. [ABSTRACT FROM AUTHOR]