Comprehensive Improved Simulated Annealing Optimization for Floorplanning of Heterogeneous 3D Networks-on-Chip.

With the rapid development of integrated circuit manufacturing processes, poor system scalability has become a prominent problem for System on Chip (SoC).To solve the bottleneck problems such as global synchronization, network on chip Networks on Chip (NoC) has emerged as a new design to tackle the increasing communication demand among elements on chips. With the development of networks-on-chip, the research has expanded from two-dimensional to three-dimensional design, and 3D networks-on-chip is a combination of 3D integration technology and 2D networks-on-chips with the advantages of both to meet the development trend of diversified chip functions. This paper presents an improved floorplanning optimization algorithm based on simulated annealing algorithm (Comprehensive Improved Simulated Annealing, hereinafter referred to as CISA algorithm) to replace the original floorplanning optimization algorithm based on simulated annealing algorithm (Simulated Annealing, hereinafter referred to as SA algorithm) to make it more applicable to the three-dimensional network-on- chip simulation. This paper describes the CISA algorithm improvement ideas and uses it on an existing 3D network-on-chip simulator with a set of classical simulation tests. The results show that the proposed CISA algorithm is better than the original SA algorithm and it is more suitable for simulations of three-dimensional networks-on-chip, especially when dealing with large scale 3D NoC. [ABSTRACT FROM AUTHOR]