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High-Performance Asymmetric Underlap Ge-pTFET With Pocket Implantation.
- Source :
-
IEEE Transactions on Electron Devices . Oct2016, Vol. 63 Issue 10, p3869-3875. 7p. - Publication Year :
- 2016
-
Abstract
- This paper reports a systematic methodology to enhance the performance of germanium p-type tunnel FETs (Ge-pTFETs) using a p+ pocket implant at the source end of the channel and an underlap region at the drain end. The numerical device simulation results show that an optimized drain-underlap region reduces the off-state leakage current ( I\mathrm{\scriptscriptstyle OFF}) of 50-nm Ge-pTFETs to about 3.27 pA/ \mu \textm without degrading the ON-current ( I\mathrm{\scriptscriptstyle ON}) , and a p+ pocket doping improves the ion of these devices to about 0.295 mA/ \mu \textm without compromising I\mathrm{\scriptscriptstyle OFF} . The analog and RF performances of the drain-underlapped Ge-pTFETs are investigated in terms of the drain current, transconductance, output resistance, intrinsic gain, cutoff frequency, and maximum frequency of oscillation for pocket-doping length varying from 0 to 6 nm. In addition, the influence of the pocket doping on the nonquasi-static performance is analyzed in terms of the gate–source and gate–drain capacitances, gate–drain resistance, and intrinsic delay time. Finally, the performance of the source-pocket drain-underlapped Ge-pTFETs in ICs is studied using a common source amplifier. [ABSTRACT FROM PUBLISHER]
- Subjects :
- *GERMANIUM
*FIELD-effect transistors
*COMPUTER simulation
*BAND gaps
*MOLYBDENUM
Subjects
Details
- Language :
- English
- ISSN :
- 00189383
- Volume :
- 63
- Issue :
- 10
- Database :
- Academic Search Index
- Journal :
- IEEE Transactions on Electron Devices
- Publication Type :
- Academic Journal
- Accession number :
- 118352377
- Full Text :
- https://doi.org/10.1109/TED.2016.2601884