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An NTF-enhanced incremental ΣΔ modulator using a SAR quantizer.
- Source :
-
Integration: The VLSI Journal . Sep2016, Vol. 55, p212-219. 8p. - Publication Year :
- 2016
-
Abstract
- In this paper, a noise transfer function (NTF) enhanced incremental sigma-delta (ΣΔ) modulator is presented. It employs a charge redistribution successive approximation register (SAR) analog-to-digital converter (ADC) in an error-feedback scheme to achieve an extra noise-shaping order. Using a multi-bit SAR quantizer not only improves the stability and power consumption but also facilitates the realization of both the adder situated in front of the quantizer and the whole error-feedback loop. As a design example, a multiplexed 2nd-order modulator based on the proposed architecture is simulated in TSMC 90 nm CMOS technology using Spectre with a 1 V single power supply. The simulation results show a signal-to-noise and distortion ratio (SNDR) of 85.3 dB within a signal bandwidth of 20 kHz (1 kHz/channel) at 5 MHz sampling frequency. The power consumption for each channel is 8.6 µW. [ABSTRACT FROM AUTHOR]
Details
- Language :
- English
- ISSN :
- 01679260
- Volume :
- 55
- Database :
- Academic Search Index
- Journal :
- Integration: The VLSI Journal
- Publication Type :
- Academic Journal
- Accession number :
- 118738997
- Full Text :
- https://doi.org/10.1016/j.vlsi.2016.06.006