Design and simulation of an ultra-low power high performance CMOS logic: DMTGDI.

An ultra-low power, high speed dual mode CMOS logic family called DMTGDI is introduced. This logic family takes over and improves main characteristics of Gate Diffusion Input (GDI) and Dual Mode Logic (DML). Simulations have been performed in 90 nm CMOS on a single bit full adder. DMTGDI shows 60% performance improvement over conventional DML, and significant reduction of power-delay product (PDP), of about 95% in static mode, and 75% in dynamic mode. Monte Carlo simulations reveal that DMTGDI is more robust under process variation comparing to conventional DML. Post layout simulation demonstrates negligible effect of parasitic elements on performance of the single bit adder. [ABSTRACT FROM AUTHOR]