Cite
Circuit Level Layout Optimization of MOS Transistor for RF and Noise Performance Improvements.
MLA
Jeon, Jongwook, and Myounggon Kang. “Circuit Level Layout Optimization of MOS Transistor for RF and Noise Performance Improvements.” IEEE Transactions on Electron Devices, vol. 63, no. 12, Dec. 2016, pp. 4674–77. EBSCOhost, https://doi.org/10.1109/TED.2016.2614275.
APA
Jeon, J., & Kang, M. (2016). Circuit Level Layout Optimization of MOS Transistor for RF and Noise Performance Improvements. IEEE Transactions on Electron Devices, 63(12), 4674–4677. https://doi.org/10.1109/TED.2016.2614275
Chicago
Jeon, Jongwook, and Myounggon Kang. 2016. “Circuit Level Layout Optimization of MOS Transistor for RF and Noise Performance Improvements.” IEEE Transactions on Electron Devices 63 (12): 4674–77. doi:10.1109/TED.2016.2614275.