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A Bias-Bounded Digital True Random Number Generator Architecture.
- Source :
-
IEEE Transactions on Circuits & Systems. Part I: Regular Papers . Jan2017, Vol. 64 Issue 1, p133-144. 12p. - Publication Year :
- 2017
-
Abstract
- Bias phenomenon has been a ubiquitous problem in the designs of digital True Random Number Generator (TRNG). Circuit performance can be improved with some auxiliary modules such as analog circuits and post-processing components, which usually involve the compromising of cost, compatibility, throughput, and security as well. In some cases only sub-optimal designs can be achieved. In this paper, by utilizing the diverse timing characteristics of different initial states, a staged-running Self-timed Ring (STR) architecture, which is able to suppress the degree of bias, is proposed. The proposed architecture is compared with some conventional free-running architectures using a Xilinx Zynq-7000 Field Programmable Gate Array (FPGA) platform for a throughput of 100 Mbps. With the increase of the ring size, the bias degree of the newly proposed structure is within a negligible level of less than 1%; whereas those of the conventional architectures can exceed 10%. Statistical tests were also conducted and the results show that the quality of randomness rises as the complexity in initial-state mapping and the ring nodes of the proposed structure increases. The test passes the National Institute of Standards and Technology (NIST) test suite with high p-values. [ABSTRACT FROM PUBLISHER]
- Subjects :
- *RANDOM number generators
*STATISTICAL bias
*ELECTRIC circuit analysis
Subjects
Details
- Language :
- English
- ISSN :
- 15498328
- Volume :
- 64
- Issue :
- 1
- Database :
- Academic Search Index
- Journal :
- IEEE Transactions on Circuits & Systems. Part I: Regular Papers
- Publication Type :
- Periodical
- Accession number :
- 120661784
- Full Text :
- https://doi.org/10.1109/TCSI.2016.2606353