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Star-EDT: Deterministic On-Chip Scheme Using Compressed Test Patterns.
- Source :
-
IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems . Apr2017, Vol. 36 Issue 4, p683-693. 11p. - Publication Year :
- 2017
-
Abstract
- This paper presents Star-EDT—a novel deterministic test compression scheme. The proposed solution seamlessly integrates with EDT-based compression and takes advantage of two key observations: 1) there exist clusters of test vectors that can detect many random-resistant faults with a cluster comprising a parent pattern and its derivatives obtained through simple transformations and 2) a significant majority of specified positions of ATPG-produced test cubes are typically clustered within a single or, at most, a few scan chains. The Star-EDT approach elevates compression ratios to values typically unachievable through conventional reseeding-based solutions. Experimental results obtained for large industrial designs, including those with a new class of test points aware of ATPG-induced conflicts, illustrate feasibility of the proposed deterministic test scheme and are reported herein. In particular, they confirm that the Star-EDT can act as a valuable form of deterministic BIST. [ABSTRACT FROM PUBLISHER]
Details
- Language :
- English
- ISSN :
- 02780070
- Volume :
- 36
- Issue :
- 4
- Database :
- Academic Search Index
- Journal :
- IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems
- Publication Type :
- Academic Journal
- Accession number :
- 122014051
- Full Text :
- https://doi.org/10.1109/TCAD.2016.2597214