Steady-state dc voltage ripple discrete analysis of PFC with estimated second-order harmonic compensation for achieving satisfactory performance.

In the conventional output voltage feedback loop design of an active power factor corrector (PFC), the bandwidth of the loop is limited to a frequency significantly lower than the input line voltage frequency. This is due to the fact that the compensator placed in the outputvoltage feedback loop is usually designed to have a narrow bandwidth in order to filter the voltage ripple of twice the line frequency coming from the PFC output dc voltage. This feedback loop is designed with this filtering effect because a relatively high ripple voltage would cause considerable distortion in the reference of the line current feedback loop. However, a low bandwidth voltage feedback loop would bring poor dynamic response which usually causes large overshoots and dips during load transient change. Therefore, a compromise is generally made for the traditional design of the output voltage feedback loop, which leads to an issue that both the steady and the dynamic behaviours of the PFC are not optimal. In this paper, mathematic model of the steady behaviour of a PFC with voltage ripple in the output-voltage feedback loop is studied using two parameters: the amplitude of the relative voltage ripple on the control output signal and its phase lag angle of the voltage feedback loop. On the basis of the analysis, a second-order voltage harmonic injection to the output-voltage feedback loop is used to eliminate the voltage harmonic components from the voltage feedback loop. Finally, the feasibility of the proposed second-order harmonic injection method was verified by simulation and experimental results. [ABSTRACT FROM AUTHOR]