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Clock Sequences for Increasing the Fault Coverage of Functional Test Sequences.
- Source :
-
IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems . Jul2017, Vol. 36 Issue 7, p1231-1235. 5p. - Publication Year :
- 2017
-
Abstract
- A functional test sequence for a design may not be effective as a manufacturing test for a logic block in the design because it achieves a low gate-level fault coverage. This paper describes a procedure for selecting a clock sequence that increases the gate-level fault coverage of a functional test sequence when it is used for testing a subset of logic blocks. The procedure deactivates the clocks to the logic blocks in the subset when a primary input vector has a negative effect on their fault coverage. The procedure is different from earlier test generation and test compaction procedures in that it increases the fault coverage without modifying the functional test sequence. It thus preserves some of the functional characteristics and the test application process for the sequence. Experimental results for benchmark circuits are presented to demonstrate the effectiveness of the procedure. [ABSTRACT FROM AUTHOR]
- Subjects :
- *LOGIC
*BOREL subsets
*USB flash drives
*BIT error rate
*MEMORY
Subjects
Details
- Language :
- English
- ISSN :
- 02780070
- Volume :
- 36
- Issue :
- 7
- Database :
- Academic Search Index
- Journal :
- IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems
- Publication Type :
- Academic Journal
- Accession number :
- 123771521
- Full Text :
- https://doi.org/10.1109/TCAD.2016.2622622