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Carbon nanotube transistors scaled to a 40-nanometer footprint.
- Source :
-
Science . 6/30/2017, Vol. 356 Issue 6345, p1369-1372. 4p. 1 Color Photograph, 2 Graphs. - Publication Year :
- 2017
-
Abstract
- The International Technology Roadmap for Semiconductors challenges the device research community to reduce the transistor footprint containing all components to 40 nanometers within the next decade. We report on a p-channel transistor scaled to such an extremely small dimension. Built on one semiconducting carbon nanotube, it occupies less than half the space of leading silicon technologies, while delivering a significantly higher pitch-normalized current density—above 0.9 milliampere per micrometer at a low supply voltage of 0.5 volts with a subthreshold swing of 85millivolts per decade. Furthermore,we show transistors with the same small footprint built on actual high-density arrays of such nanotubes that deliver higher current than that of the best-competing silicon devices under the same overdrive,without any normalization. We achieve this using low-resistance end-bonded contacts, a high-purity semiconducting carbon nanotube source, and self-assembly to pack nanotubes into full surface-coverage aligned arrays. [ABSTRACT FROM AUTHOR]
Details
- Language :
- English
- ISSN :
- 00368075
- Volume :
- 356
- Issue :
- 6345
- Database :
- Academic Search Index
- Journal :
- Science
- Publication Type :
- Academic Journal
- Accession number :
- 123879183
- Full Text :
- https://doi.org/10.1126/science.aan2476