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Physical-Model Guided Design on Transistor Test Structures for Extracting Metal Charging Design Rules.
- Source :
-
IEEE Transactions on Electron Devices . Apr2017, Vol. 64 Issue 4, p1674-1682. 9p. - Publication Year :
- 2017
-
Abstract
- Physical-model guided design on transistor test structures aiming for extracting backend metal charging design rules is demonstrated for the first time. Based on experimental data from a six-metal-layer technology, the demonstration shows such design methodology to be feasible. The methodology enables adequate design for the test structures from which a complete set of metal charging design rules can be extracted for a given process technology. This paper concludes that a significant reduction in the number of the required test structures and accordingly a large saving for test chip layout space during process development can be realized with the new design methodology. The number of the design-rule-extraction test structures could be reduced by a half for a six-metal-layer technology and by 77% for a thirteen-metal-layer layer technology, with a minimum number as low as four per transistor type, gate oxide thickness, and gate protection option if such methodology is adopted. The advantage inherited in the new methodology is delineated. [ABSTRACT FROM PUBLISHER]
Details
- Language :
- English
- ISSN :
- 00189383
- Volume :
- 64
- Issue :
- 4
- Database :
- Academic Search Index
- Journal :
- IEEE Transactions on Electron Devices
- Publication Type :
- Academic Journal
- Accession number :
- 124146676
- Full Text :
- https://doi.org/10.1109/TED.2017.2667684