Bias polarity Dependent Effects of P+Floating Gate EEPROMs.

EEPROM devices with either N-type or P-type floating gate were fabricated and characterized. Program/erase speeds and stress-induced leakage current-related retention characteristics for both types of devices are explained. Discrepancies between previously published reports of P-type floating gate devices and PMOS gate current measurements are resolved. The feasibility of integrating P-type floating gate EEPROMs in high density memory arrays is examined. [ABSTRACT FROM AUTHOR]