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Bias polarity Dependent Effects of P+Floating Gate EEPROMs.
- Source :
-
IEEE Transactions on Electron Devices . Feb2004, Vol. 51 Issue 2, p282-285. 4p. - Publication Year :
- 2004
-
Abstract
- EEPROM devices with either N-type or P-type floating gate were fabricated and characterized. Program/erase speeds and stress-induced leakage current-related retention characteristics for both types of devices are explained. Discrepancies between previously published reports of P-type floating gate devices and PMOS gate current measurements are resolved. The feasibility of integrating P-type floating gate EEPROMs in high density memory arrays is examined. [ABSTRACT FROM AUTHOR]
Details
- Language :
- English
- ISSN :
- 00189383
- Volume :
- 51
- Issue :
- 2
- Database :
- Academic Search Index
- Journal :
- IEEE Transactions on Electron Devices
- Publication Type :
- Academic Journal
- Accession number :
- 12437936
- Full Text :
- https://doi.org/10.1109/TED.2003.821702