Case Study of a Hybrid Optoelectronic Limiting Receiver.

The systematic design analysis of a hybrid optoelectronic limiting receiver is presented. The limiting receiver was designed in the IBM 130-nm CMOS process and side-by-side wire bonded to a commercial high-speed InGaAs/InP PIN photodiode. The CMOS die and the optical die were chip-on-board (COB) mounted on the Printed Circuit Board. Partition between small signal in the linear region and large-signal in the limiting region is emphasized. The signal edges can get sharpened in the limiting region although the front-end circuit is bandwidth-limited. When tested with a PRBS-31 pattern, the prototype achieved a bit-error rate of 10^-12 at the sensitivity level of −3.2-dBm Mach-Zehnder Modulator optical modulation amplitude at 4 Gb/s. Conclusions derived from this paper can provide insights to guide other optical limiting receiver design and testing at higher speeds. [ABSTRACT FROM PUBLISHER]