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Case Study of a Hybrid Optoelectronic Limiting Receiver.
- Source :
-
IEEE Transactions on Circuits & Systems. Part I: Regular Papers . Oct2017, Vol. 64 Issue 10, p2797-2805. 9p. - Publication Year :
- 2017
-
Abstract
- The systematic design analysis of a hybrid optoelectronic limiting receiver is presented. The limiting receiver was designed in the IBM 130-nm CMOS process and side-by-side wire bonded to a commercial high-speed InGaAs/InP PIN photodiode. The CMOS die and the optical die were chip-on-board (COB) mounted on the Printed Circuit Board. Partition between small signal in the linear region and large-signal in the limiting region is emphasized. The signal edges can get sharpened in the limiting region although the front-end circuit is bandwidth-limited. When tested with a PRBS-31 pattern, the prototype achieved a bit-error rate of 10^-12 at the sensitivity level of −3.2-dBm Mach-Zehnder Modulator optical modulation amplitude at 4 Gb/s. Conclusions derived from this paper can provide insights to guide other optical limiting receiver design and testing at higher speeds. [ABSTRACT FROM PUBLISHER]
Details
- Language :
- English
- ISSN :
- 15498328
- Volume :
- 64
- Issue :
- 10
- Database :
- Academic Search Index
- Journal :
- IEEE Transactions on Circuits & Systems. Part I: Regular Papers
- Publication Type :
- Periodical
- Accession number :
- 125422016
- Full Text :
- https://doi.org/10.1109/TCSI.2017.2695369