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Pre-Charged Local Bit-Line Sharing SRAM Architecture for Near-Threshold Operation.
- Source :
-
IEEE Transactions on Circuits & Systems. Part I: Regular Papers . Oct2017, Vol. 64 Issue 10, p2737-2747. 11p. - Publication Year :
- 2017
-
Abstract
- In this paper, a pre-charged local bit-line sharing (PCLBS) static random access memory (SRAM) for near-threshold operation is proposed. In previous local bit-line sharing SRAMs, such as average-8T and full-swing local bit-line (FSLB) SRAMs, multiple bit-cells share a local bit-line pair with a small capacitance for high read stability. However, the average-8T SRAM has a considerably large delay because the full development of the local bit-line cannot be achieved. On the other hand, the FSLB SRAM reduces the delay but requires a timing constraint of control signals to achieve sufficient read sensing margin. The proposed PCLBS SRAM achieves high read speed by fully developing local bit-line pair without a timing constraint. Furthermore, the proposed PCLBS SRAM enhances the read stability and the write ability by, respectively, applying a pre-charged local bit-line scheme and transmission gates in write paths. Based on a 22-nm FinFET technology, the FSLB and proposed PCLBS SRAM have the minimum operating voltages of 0.44 and 0.4 V, respectively, while achieving the $5\sigma$ target read stability and write ability yields. Compared with the FSLB SRAM, the proposed PCLBS SRAM consumes 21% less energy at each minimum operating voltage and has 57% smaller read delay at the operating voltage of 0.4 V. [ABSTRACT FROM PUBLISHER]
Details
- Language :
- English
- ISSN :
- 15498328
- Volume :
- 64
- Issue :
- 10
- Database :
- Academic Search Index
- Journal :
- IEEE Transactions on Circuits & Systems. Part I: Regular Papers
- Publication Type :
- Periodical
- Accession number :
- 125422022
- Full Text :
- https://doi.org/10.1109/TCSI.2017.2702587