A Fourier-based single phase PLL algorithm: Design, analysis, and implementation in FPGA controller.

Control of grid tied inverter attached to the distribution level single phase grid needs to be robust in order to be resilient to grid disturbances and dynamics, without dissension of output power quality. This calls for an improvement of existing synchronization techniques whose bedrock is the phase locked loop algorithm. The paper proposes a phase and frequency estimation technique which shows excellent performance to dynamic changes and has high distortion rejection capability. The technique used interpolated FFT which estimates the frequency followed by sample value adjustment which gives highly accurate phase estimate by transforming off-nominal frequency samples into nominal data points. The technique being a discrete algorithm, system identification is performed to estimate the transfer function model upon which stability and dynamic analysis are performed. A comparative analysis with SOGI PLL, PARK PLL, TPFA PLL, and Fourier PLL shows the superiority of the proposed technique in terms of accurate steady and dynamic state estimation capacity during grid disturbance and faults. The study of the computational complexity and applicability in FPGA controller reveals the feasibility of implementation of the technique in low level FPGA controllers. The proposed algorithm has been implemented in NI cRIO FPGA controller to tap real-time signals and control the inverter. Thus, this PLL is suitable for fault-ride-through operation of the inverter in feeding power to the distribution grid. [ABSTRACT FROM AUTHOR]