Wafer Level Integration of 3-D Heat Sinks in Power ICs.

MLA

Para, Isabella, et al. “Wafer Level Integration of 3-D Heat Sinks in Power ICs.” IEEE Transactions on Electron Devices, vol. 64, no. 10, Oct. 2017, pp. 4226–32. EBSCOhost, https://doi.org/10.1109/TED.2017.2732733.

APA

Para, I., Marasso, S. L., Cocuzza, M., Ferrero, S., Scaltrito, L., Pirri, C. F., Perrone, D., Gentile, M. G., Sanfilippo, C., Richieri, G., Merlin, L., & Pugliese, D. (2017). Wafer Level Integration of 3-D Heat Sinks in Power ICs. IEEE Transactions on Electron Devices, 64(10), 4226–4232. https://doi.org/10.1109/TED.2017.2732733

Chicago

Para, Isabella, S. L. Marasso, M. Cocuzza, S. Ferrero, L. Scaltrito, C. F. Pirri, D. Perrone, et al. 2017. “Wafer Level Integration of 3-D Heat Sinks in Power ICs.” IEEE Transactions on Electron Devices 64 (10): 4226–32. doi:10.1109/TED.2017.2732733.